EP0191612A2 — Semiconductor memory device having stacked-capaci…

Claim 1

Independent Claim 266 words

A semiconductor memory device comprising: a substrate (21); a plurality of word lines; a plurality of bit lines (33); and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a capacitor (C2) for storing data and a transistor (Q2) cooperably connected to said capacitor for transferring data to said capacitor; said word lines being formed by a first conductive layer (24-1 to 24-4); said transistor in each said memory cell including a gate connected to or formed by one of said word lines (24-2), a gate insulating layer (23-2) and source and drain regions (27 and 28); each of said memory cells having a first insulating layer (25-2) covering said gate of said transistor, and a second insulating layer (26-3) covering another word line (24-3) adjacent to said one word line (24-2), the second insulating layer having a larger thickness than that of said first insulating layer covering said gate; said capacitor in each said memory cell including: a second conductive layer (29-2) which is in contact with one of said source and drain regions of said transistor in the memory cell, which extends onto the gate of said transistor over said first insulating layer, and which covers said second insulating layer; a third insulating layer (30-2)formed on said second conductive layer; and a third conductive layer (31) ' extending over said third insulating layer; one of said bit lines being connected to the other of said source and drain regions of said transistor in each of said memory cells.

Claim 2

Dependent Claim 266 words

A semiconductor memory device comprising: a substrate (21); a plurality of word lines; a plurality of bit lines (33); and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a capacitor (C2) for storing data and a transistor (Q2) cooperably connected to said capacitor for transferring data to said capacitor; said word lines being formed by a first conductive layer (24-1 to 24-4); said transistor in each said memory cell including a gate connected to or formed by one of said word lines (24-2), a gate insulating layer (23-2) and source and drain regions (27 and 28); each of said memory cells having a first insulating layer (25-2) covering said gate of said transistor, and a second insulating layer (26-3) covering another word line (24-3) adjacent to said one word line (24-2), the second insulating layer having a larger thickness than that of said first insulating layer covering said gate; said capacitor in each said memory cell including: a second conductive layer (29-2) which is in contact with one of said source and drain regions of said transistor in the memory cell, which extends onto the gate of said transistor over said first insulating layer, and which covers said second insulating layer; a third insulating layer (30-2)formed on said second conductive layer; and a third conductive layer (31) ' extending over said third insulating layer; one of said bit lines being connected to the other of said source and drain regions of said transistor in each of said memory cells.

Claim 3

Dependent Claim 75 words

A semiconductor memory device according to claim 1, wherein said second insulating layer (26-2A, 26-2B) is also provided on both sides of said gate, and wherein said first insulating layer (25-3) is also provided on said adjacent word line (24-3), and said second insulating layer (26-3) is provided on said first insulating layer over said adjacent word line, so as to electrically isolate said word lines from said bit lines and said second conductive layer.

Claim 4

Dependent Claim 27 words

A semiconductor memory device according to claim 1 or 2, wherein a thickness of said second insulating layer is greater than that of said first insulating layer.

Claim 5

Dependent Claim 57 words

A semiconductor memory device according to claim 3, wherein said first insulating layer is made of silicon oxide or silicon nitride and has a thickness of approximately 200 nm (2000 A) , and wherein said second insulating layer is made of silicon oxide or silicon nitride and has a thickness of approximately 0 400 nm (4000 A).

Claim 6

Dependent Claim 74 words

A semiconductor memory device according to claim 1,2,3, or 4, wherein said device further comprises an additional conductive layer (29-1) directly connected to the other of said source and drain regions of said transistor in the memory cell and extending onto the gate of the transistor over said first insulating layer covering said gate, each said bit line being connected to the other of said source and drain regions through said additional conductive layer.

Claim 7

Dependent Claim 86 words

A semiconductor memory device according to claim 5, wherein said additional conductive layer, formed on the other of said source and drain regions of said transistor and extending onto said gate of the adjoining transistor over said first insulating layer means covering said gate, has a predetermined thickness at the region extending onto the gate and a predetermined width to facilitate formation of a contact window for electrically connecting said bit line with the other of said source and drain regions through said additional conductive layer.

Claim 8

Dependent Claim 28 words

A semiconductor memory device according to claim 5 or 6, wherein the thickness of the additional conductive layer is approximately equal to that of the second conductive layer.

Claim 9

Dependent Claim 36 words

A semiconductor memory device according to claim 5 ,6 or 7, wherein -the additional conductive layer in each said memory cell also extends over one of the adjacent word lines other than its own gate. preceding

Claim 10

Dependent Claim 52 words

A semiconductor memory device according to any preceding claim , wherein said semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions and a gate electrode which is entirely covered by said second insulating layer, said source and drain regions being directly connected to wiring lines.

Claim 11

Independent Claim 226 words

A method for manufacturing a semiconductor memory device having a substrate, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell positioned at an intersection defined by one of said word lines and said bit lines and including a capacitorkstoring data and a transistor operatively connected to said capacitor for transferring data to said capacitor, including the steps of: forming a first conductive layer (24) on an insulating layer (23) on said substrate (21) and a first insulating layer (25) on said first conductive layer; patterning said first insulating layer to define a plurality of word lines of said first conductive layer; patterning said first conductive layer with masking by said patterned first insulating layer to form a plurality of word lines; forming a second insulating layer (26) on the whole substrate; and etching said second insulating layer with protecting portions of said second insulating layer on said plurality of word lines to be formed thereor. from the etching to expose drain and source forming regions of said transistor in said substrate so that a thickness of insulating layer including unetched first and second insulating layers on said plurality of word lines on which said capacitor is to be formed thereon is greater than that of other insulating layers remaining after said etching on other word lines.

Claim 12

Independent Claim 226 words

A method for manufacturing a semiconductor memory device having a substrate, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell positioned at an intersection defined by one of said word lines and said bit lines and including a capacitorkstoring data and a transistor operatively connected to said capacitor for transferring data to said capacitor, including the steps of: forming a first conductive layer (24) on an insulating layer (23) on said substrate (21) and a first insulating layer (25) on said first conductive layer; patterning said first insulating layer to define a plurality of word lines of said first conductive layer; patterning said first conductive layer with masking by said patterned first insulating layer to form a plurality of word lines; forming a second insulating layer (26) on the whole substrate; and etching said second insulating layer with protecting portions of said second insulating layer on said plurality of word lines to be formed thereor. from the etching to expose drain and source forming regions of said transistor in said substrate so that a thickness of insulating layer including unetched first and second insulating layers on said plurality of word lines on which said capacitor is to be formed thereon is greater than that of other insulating layers remaining after said etching on other word lines.

Claim 13

Dependent Claim 201 words

A method for manufacturing according to claim 10, further including the steps of, forming said transistor having source and drain regicns (27, 28) formed in said substrate and a gate electrode (24-2) of said first conductive layer cn said substrate; forming a second conductive layer (29) extending over said second insulating layers on said word lines, said second conductive layer being in direct contact with one of said source and drain regions of said transistor and being electrically isolated from said gate electrodes and said word lines through said first and second insulating layers; removing a portion of said second conductive layer above said gate electrode, the remaining portion of said conductive layer extending over said gate electrode, to separate said second conductive layer into a capacitor electrode and an interface conductive layer having an island-form on said one of source and drain regions; forming a third insulating layer (30) of dielectric material on at least said capacitor electrode; forming a third conductive layer as another capacitor electrode on at least said third insulating layer; forming a contact window on said interface conductive layer with self-alignment; and forming said bit line connected to said interface conductive layer at said contact window.

Claim 14

Independent Claim 199 words

A method for manufacturing according to 10 or claim/11, further including a step forming peripheral circuits for said plurality of memory cells, including a plurality of sense amplifiers each having at least one another transistor, said peripheral circuits forming step including the steps of, forming a conductive layer (52) corresponding to said first conductive layer (24) on said insulating layer (23), simultaneously to forming said first conductive layer, and an insulating layer corresponding to said first insulating layer (25), on said conductive layer, simultaneously to the forming of said first insulating layer; patterning said cenductive layer to define a plurality of wiring lines for connecting gates of said another transistors, simultaneously to patterning of said first conductive layer; forming another insulating layer corresponding to said second layer (26) on the whole of said peripheral circuits forming region, simultaneously to forming second insulating layer; etching said another insulating layer to expose drain and source forming regions of said another transistors; forming said another transistor having source and drain regions (55, 56) and a gate electrode of said conductive layer (52); and forming other conductive layers (58-1, 58-2) in direct contact with said source and drain regions of said another transistor.

Semiconductor memory device having stacked-capacitor type memory cells and a manufacturing method for the same

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