EP0161850A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device having stacked-capacitor type memory cells and manufacturing method for the same
Assignee: Fujitsu Ltd
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Filing: 1985-04-26
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Granted: —
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Expires: 2005-04-26
Abstract
Abstract A semiconductor memory device including: a substrate (21), a plurality of word lines (26), a plurality of bit lines (34); and a plurality of memory cells, each positioned at an intersection defined by one of the word lines (26) and one of the bit lines (34) and including a transfer transistor (Tr) and a capacitor (28, 30, 31). Each of the memory cells has a first insulating layer (27) covering a gate of the transfer transistor (Tr). The capacitor (28, 30, 31) in each memory cell includes a second conductive layer (28) which contacts one of the source and drain regions of the transfer transistor in the memory cell and extends over the gate of the transfer transistor through the first insulating layer (27), a second insulating layer (30) formed on the second conductive layer (28), and a third conductive layer (31), extending over the second insulating layer (30). The semiconductor memory device further includes an additional conductive layer (29) directly connected to the other of the source and drain regions of the transfer transistor in the memory cell and extending over the gates of the adjoining transfer transistors through the first insulating layers (27) covering thereon. Each bit line (34) is connected to the other of the source and drain regions through the additional conductive layer (29). A method for manufacturing a semiconductor memory device having the above construction is also disclosed.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Tomio Nakano
- 👤 Masao Nakano
- 👤 Kimiaki Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 06:11
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/05; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
221 words
A semiconductor memory device comprising: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a transfer transistor and a capacitor; said word lines being formed by a first conductive layer, said transfer transistor in each said memory cell comprising a gate connected to one of said word linesand formed by said first conductive layer, and source and drain regions, each of said memory cells having a first insulating layer covering said gate of said transfer transistor, said capacitor in each said memory cell comprising a second conductive layer which contacts one of said source and drain regions of said transfer transistor in the memory cell, a second insulating layer formed on said second conductive layer, and a third conductive layer, extending over said second insulating layer, said semiconductor memory device further comprising an additional conductive layer directly connected to the other of said source and drain regions of the transfer transistor in the memory cell and extending over the gate of the adjoining transfer transistors through the first insulating layers covering thereon, a said bit line being connected to the other of said source and drain regions through said additional conductive layer.
Claim 2
Dependent Claim
221 words
A semiconductor memory device comprising: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of said word lines and one of said bit lines and including a transfer transistor and a capacitor; said word lines being formed by a first conductive layer, said transfer transistor in each said memory cell comprising a gate connected to one of said word linesand formed by said first conductive layer, and source and drain regions, each of said memory cells having a first insulating layer covering said gate of said transfer transistor, said capacitor in each said memory cell comprising a second conductive layer which contacts one of said source and drain regions of said transfer transistor in the memory cell, a second insulating layer formed on said second conductive layer, and a third conductive layer, extending over said second insulating layer, said semiconductor memory device further comprising an additional conductive layer directly connected to the other of said source and drain regions of the transfer transistor in the memory cell and extending over the gate of the adjoining transfer transistors through the first insulating layers covering thereon, a said bit line being connected to the other of said source and drain regions through said additional conductive layer.
Claim 3
Dependent Claim
82 words
A semiconductor memory device according to claim 1, wherein said additional conductive layer, formed on the other of said source and drain regions of the transfer transistor and extending over the gate of the adjoining transfer transistors through the first insulating layers covering thereon, has a predetermined thickness at the extended-over region and a predetermined width to ensure forming a contact window for electrically connecting said bit line with the other of said source and drain regions through the additional conductive layer.
Claim 4
Dependent Claim
26 words
A semiconductor memory device according to claim 2, wherein the thickness of the additional conductive layer is approximately equal to that of the second conductive layer.
Claim 5
Dependent Claim
41 words
A semiconductor memory device according to claim 1, 2 or 3, wherein each of said word lines is covered by said first insulating layer to electrically isolate each of said word lines from said bit lines and said second conductive layer.
Claim 6
Dependent Claim
33 words
A semiconductor memory device according to any preceding claim, wherein the second conductive layer in each said memory cell extends over one of the adjacent word lines other than its own word line.
Claim 7
Dependent Claim
51 words
A semiconductor memory device according to preceding claim, any/ wherein said semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions and a gate electrode which is entirely covered by said first insulating layer, said source and drain regions being directly connected to wiring lines.
Claim 8
Independent Claim
218 words
A method for manufacturing a semiconductor memory device having a substrate, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell positioned at an intersection defined by one of said word lines and said bit lines and including a transfer transistor and a capacitor, including the steps of: forming said transfer transistor having source and drain regions formed in said substrate and a gate electrode of a first conductive layer on said substrate; forming a second conductive layer extending over the transfer transistor, said second conductive layer directly contacting said source and drain regions of the transfer transistor and being electrically isolated from said gate electrode through a first insulating layer; removing a portion of said second conductive layer above said gate electrode, the remaining portion of said conductive layer extending over said gate electrode, to separate said second conductive layer into a capacitor electrode and an interface conductive layer having an island-form; forming a second insulating layer of dielectric material on at least said capacitor electrode; forming a third conductive layer as another capacitor electrode on at least said second insulating layer; forming a contact window in said interface conductive layer with self-alignment; and forming a bit line connected to said interface conductive layer at said contact window.
Claim 9
Independent Claim
218 words
A method for manufacturing a semiconductor memory device having a substrate, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell positioned at an intersection defined by one of said word lines and said bit lines and including a transfer transistor and a capacitor, including the steps of: forming said transfer transistor having source and drain regions formed in said substrate and a gate electrode of a first conductive layer on said substrate; forming a second conductive layer extending over the transfer transistor, said second conductive layer directly contacting said source and drain regions of the transfer transistor and being electrically isolated from said gate electrode through a first insulating layer; removing a portion of said second conductive layer above said gate electrode, the remaining portion of said conductive layer extending over said gate electrode, to separate said second conductive layer into a capacitor electrode and an interface conductive layer having an island-form; forming a second insulating layer of dielectric material on at least said capacitor electrode; forming a third conductive layer as another capacitor electrode on at least said second insulating layer; forming a contact window in said interface conductive layer with self-alignment; and forming a bit line connected to said interface conductive layer at said contact window.
References Cited (Backward Citations)
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