EP0098165A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1983-06-29
•
Granted: —
•
Expires: 2003-06-29
Abstract
Abstract The soft-error rate in an MOS d-RAM semiconductor memory device can be reduced by an impurity-doped getter region (14) of conductivity opposite to that of a substrate 11, formed in the substrate 11 below and in contact with a field oxide layer 12 on the substrate 11. This getter region 14 collects minority carriers produced by incident radiation and so shields the memory cell capacitor from these minority carriers as well as by forming a capacitor storage on the field oxide layer 12. This device has an advantage of not decreasing the density of a memory cell array.
Inventors
- 👤 Masao Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 08:41
CPC Classifications
H; H10; H10W; H10W15/00; H10B; H10B12/00; H10B12/30; H10W15/01; H10W42/00; H10W42/20; H10W42/25
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
84 words
A semiconductor memory device including memory cells comprising a switching transistor and a storage capacitor (15, 16, 17) characterised in that the storage capacitor (15, 161j 17) is formed on an insulating layer (12) on a semiconductor substrate (11) and in that the memory cells have in the substrate (11) an impurity-doped getter region (14) of a conductivity opposite to that of the substrate (11) formed below and in contact with the insulating layer (12), for collecting minority carriers generated in the substrate (11).
Claim 2
Dependent Claim
84 words
A semiconductor memory device including memory cells comprising a switching transistor and a storage capacitor (15, 16, 17) characterised in that the storage capacitor (15, 161j 17) is formed on an insulating layer (12) on a semiconductor substrate (11) and in that the memory cells have in the substrate (11) an impurity-doped getter region (14) of a conductivity opposite to that of the substrate (11) formed below and in contact with the insulating layer (12), for collecting minority carriers generated in the substrate (11).
Claim 3
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein the impurity-doped getter region (14) for collecting minority carriers is connected to one of the power supply terminals.
Claim 4
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein the impurity-doped getter regions (14) for collecting minority carriers of a plurality of memory cells are connected to each other but the group of interconnected regions (14) are in an electrically floating state.
Claim 5
Dependent Claim
44 words
A semiconductor device according to claims 1, 2 or 3, wherein the getter region (14) is surrounded by a channel cut region (13) highly doped with an impurity and having a conductivity opposite that of the getter region (14) in the semiconductor substrate (11).
Claim 6
Dependent Claim
84 words
A semiconductor memory device according to any one of the preceding claims, wherein the storage capacitor comprises two electrode layers (15, 17) of polysilicon, a metal silicide, or one of each, sandwiching an insulating layer (16) of silicon dioxide or silicon nitride or polysilicon or tantalum oxide, the storage capacitor being formed on a silicon dioxide layer (12) on a silicon semiconductor substrate (11), the lower electrode layer (15) of the storage capacitor making contact with an active region (18) of the substrate (11).
Claim 7
Dependent Claim
49 words
A semiconductor memory device according to any one of the preceding claims, wherein the semiconductor substrate (11) is a p-type silicon semiconductor substrate and wherein the getter region (14) is formed by implantation of arsenic ions into the p-type silicon semiconductor substrate adjacent the surface of the substrate (11).
Claim 8
Dependent Claim
102 words
A semiconductor device according to claim 4, wherein the insulating layer (12) between the storage capacitor and the getter region (14) is thick at its peripheral portion and thin at its central portion, the channel cut region (13) being below the thick peripheral portion, the getter region (14) being below the thin central portion, so that an electrode (15) of the storage capacitor on the insulating layer (12), the thin central portion of the insulating layer (12), and the impurity-doped getter region (14) function as a capacitor, resulting in an increase of the capacity- of the storage capacitor of the memory cell.
Claim 9
Dependent Claim
37 words
A semiconductor device according to claim 7, wherein both the thick and thin portions of the insulating layer (12) are formed by oxidation of the corresponding portions of the surface of the semiconductor substrate (11) of silicon.
Claim 10
Dependent Claim
45 words
A semiconductor device according to claims 7 or 8, wherein the insulating layer (12) having thick and thin thickness has an entirely flat upper surface and a major. part of the thick peripheral portion of the insulating layer (12) is located in the substrate (11).
Claim 11
Dependent Claim
65 words
A semiconductor device according to claim 9, wherein the thick peripheral portion of the insulating layer is formed by selectively etching a silicon semiconductor substrate (11) to form an aperture (41, Figure 24), oxidising the surface (42) of the silicon substrate (11) in the aperture (41), filling the aperture (41) with the polysilicon (43) and oxidising the top surface (44) of the filled polysilicon (43).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.