US5561307A
Expired / Lapsed
US
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Ferroelectric integrated circuit
Assignee: Symetrix Corp
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Filing: 1994-07-18
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Granted: 1996-10-01
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Expires: 2014-07-18
Abstract
Abstract An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.
Inventors
- 👤 Takashi Mihara
- 👤 Hiroyuki Yoshimori
- 👤 Hitoshi Watanabe
- 👤 Larry D. McMillan
- 👤 Carlos P. de Araujo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:45
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/682
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
215 words
A ferroelectric integrated circuit comprising: a semiconducting substrate having a transistor source region and a transistor drain region; a transistor formed on said substrate, said transistor including a transistor gate operably positioned between said source region and said drain region; an insulating layer overlying said transistor gate; a contact hole passing through said insulating layer to said substrate proximal to one of said source region and said drain region; a conducting barrier layer at least partially overlying said insulating layer and said transistor gate and in electrical contact with said substrate through said contact hole, said conducting barrier layer having a contact hole portion received within said contact hole; a ferroelectric device including a ferroelectric layer overlying said conducting barrier layer above said contact hole and at least partially overlying said transistor gate; and wherein said ferroelectric device comprises a ferroelectric capacitor comprising: a capacitor bottom electrode having said ferroelectric layer formed on said bottom electrode, and a capacitor top electrode formed on said ferroelectric layer, and wherein the distance between the end of said capacitor bottom electrode immediately under the end of said ferroelectric layer and the end of said capacitor top electrode immediately above the end of said ferroelectric layer is longer that the thickness of said ferroelectric layer perpendicular to said electrodes.
Claim 2
Dependent Claim
215 words
A ferroelectric integrated circuit comprising: a semiconducting substrate having a transistor source region and a transistor drain region; a transistor formed on said substrate, said transistor including a transistor gate operably positioned between said source region and said drain region; an insulating layer overlying said transistor gate; a contact hole passing through said insulating layer to said substrate proximal to one of said source region and said drain region; a conducting barrier layer at least partially overlying said insulating layer and said transistor gate and in electrical contact with said substrate through said contact hole, said conducting barrier layer having a contact hole portion received within said contact hole; a ferroelectric device including a ferroelectric layer overlying said conducting barrier layer above said contact hole and at least partially overlying said transistor gate; and wherein said ferroelectric device comprises a ferroelectric capacitor comprising: a capacitor bottom electrode having said ferroelectric layer formed on said bottom electrode, and a capacitor top electrode formed on said ferroelectric layer, and wherein the distance between the end of said capacitor bottom electrode immediately under the end of said ferroelectric layer and the end of said capacitor top electrode immediately above the end of said ferroelectric layer is longer that the thickness of said ferroelectric layer perpendicular to said electrodes.
Claim 3
Dependent Claim
40 words
An integrated circuit as in claim 1 wherein said barrier layer comprises a material selected from a group consisting of: titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, and polycide.
Claim 4
Dependent Claim
19 words
An integrated circuit as in claim 1 wherein said barrier layer comprises said bottom electrode of said ferroelectric capacitor.
Claim 5
Dependent Claim
45 words
An integrated circuit as in claim 3 and further including an oxide layer less than 5 nm thick located between said barrier layer and said ferroelectric layer and wherein said barrier layer comprises a material selected from a group consisting of silicon, silicide, and polycide.
Claim 6
Dependent Claim
20 words
An integrated circuit as in claim 1 wherein a step is formed in the outer edge of said ferroelectric layer.
Claim 7
Dependent Claim
22 words
An integrated circuit as in claim 1 and further including an ohmic contact material located between said barrier layer and said substrate.
Claim 8
Dependent Claim
17 words
An integrated circuit as in claim 1 wherein said the outer edge of said capacitor is tapered.
Claim 9
Dependent Claim
130 words
A ferroelectric integrated circuit comprising: a semiconducting substrate having a transistor source region and a transistor drain region; a transistor formed on said substrate, said transistor including a gate operably positioned between said source region and said drain region; an insulating layer overlying said transistor gate and at least a portion of said substrate; a ferroelectric capacitor including a bottom electrode including a conducting barrier layer, a ferroelectric layer, and a top electrode; and said bottom electrode of said ferroelectric capacitor electrically contacting one of said source region and said drain region and further including an oxide layer less than 5 nm thick located between said barrier layer and said ferroelectric layer and wherein said barrier layer comprises a material selected from a group consisting of silicon, silicide, and polycide.
Claim 10
Dependent Claim
130 words
A ferroelectric integrated circuit comprising: a semiconducting substrate having a transistor source region and a transistor drain region; a transistor formed on said substrate, said transistor including a gate operably positioned between said source region and said drain region; an insulating layer overlying said transistor gate and at least a portion of said substrate; a ferroelectric capacitor including a bottom electrode including a conducting barrier layer, a ferroelectric layer, and a top electrode; and said bottom electrode of said ferroelectric capacitor electrically contacting one of said source region and said drain region and further including an oxide layer less than 5 nm thick located between said barrier layer and said ferroelectric layer and wherein said barrier layer comprises a material selected from a group consisting of silicon, silicide, and polycide.
Claim 11
Dependent Claim
41 words
An integrated circuit as in claim 8 wherein said capacitor top electrode, said ferroelectric layer, and said capacitor bottom electrode have an outer end tapered at an angle ranging from 30° to 70° relative to a line perpendicular to said electrodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |