US4360896A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write mode circuitry for photovoltaic ferroelectric memory cell
Assignee: United States Department of the Army
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Filing: 1981-01-30
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Granted: 1982-11-23
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Expires: 2001-01-30
Abstract
Abstract Non-volatile semiconductor matrix random access and electrically alterablerogrammable read-only memories are disclosed. Each memory cell of the matrix memory includes a photovoltaic ferroelectric element which is remanently polarized with a write signal, and which when illuminated, produces a photovoltage which causes a field effect transistor to assume one of two states. Variable impedance means, for example, at least a diode or a breakdown diode is connected in each cell for providing a low impedance when the write gate pulse is applied to the photovoltaic ferroelectric element and for providing a high impedance when the photovoltage produced by the photovoltaic ferroelectric element is applied to the field effect transistor gate. If power to the memory is lost, by illuminating the photovoltaic ferroelectric element, the field effect transistor may be caused to assume the state which it was in before loss of power.
Inventors
- 👤 Philip S. Brody
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/42; G11C16/00; G11C16/02; G11C16/04; H; H10; H10B; H10B53/00; G11C11/223
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
155 words
A memory, comprising, solid state switch means capable of assuming one of two states dependent on a bias signal which is to be applied thereto, photovoltaic-ferroelectric means for storing information regarding said bias signal, which information is stored in the form of a remanent polarization in one of two possible directions, means for writing said information into said photovoltaic-ferroelectric means, illumination means for illuminating said photovoltaic-ferroelectric means when it is desired to generate said bias signal, means for applying said generated bias signal to said solid state switch means, and variable impedance means connected to said photovoltaic-ferroelectric means and said switch means for assuming a relatively low impedance when said information is written into said photovoltaic-ferroelectric means so that a relatively large write voltage appears across said photovoltaic-ferroelectric means and for assuming a relatively high impedance when said bias signal is generated, to allow said bias signal to be effectively applied to said switch means.
Claim 2
Dependent Claim
155 words
A memory, comprising, solid state switch means capable of assuming one of two states dependent on a bias signal which is to be applied thereto, photovoltaic-ferroelectric means for storing information regarding said bias signal, which information is stored in the form of a remanent polarization in one of two possible directions, means for writing said information into said photovoltaic-ferroelectric means, illumination means for illuminating said photovoltaic-ferroelectric means when it is desired to generate said bias signal, means for applying said generated bias signal to said solid state switch means, and variable impedance means connected to said photovoltaic-ferroelectric means and said switch means for assuming a relatively low impedance when said information is written into said photovoltaic-ferroelectric means so that a relatively large write voltage appears across said photovoltaic-ferroelectric means and for assuming a relatively high impedance when said bias signal is generated, to allow said bias signal to be effectively applied to said switch means.
Claim 3
Dependent Claim
42 words
The memory of claim 1, wherein said solid state switch means includes a control element and said means for writing said information includes signal generating means, and wherein said photovoltaic-ferroelectric means is connected between said signal generating means and said control element.
Claim 4
Dependent Claim
15 words
The memory of claim 1, wherein said variable impedance means comprises at least a diode.
Claim 5
Dependent Claim
14 words
The memory of claim 3, wherein said at least a diode comprises two diodes.
Claim 6
Dependent Claim
17 words
The memory of claim 3, wherein said at least a diode comprises at least a breakdown diode.
Claim 7
Dependent Claim
18 words
The memory of claim 5, wherein said at least a breakdown diode comprises a pair of breakdown diodes.
Claim 8
Dependent Claim
28 words
The memory of claim 1, wherein said solid state switch means comprises a JFET and wherein said at least a diode comprises the gate junction of the JFET.
Claim 9
Dependent Claim
14 words
The memory of claim 1, wherein said means for writing includes bilateral switch means.
Claim 10
Dependent Claim
19 words
A matrix memory comprising a plurality of memory cells, each cell being a memory as recited in claim 1.
Claim 11
Dependent Claim
27 words
A matrix memory as recited in claim 9, wherein said means for writing includes a bilateral switch means associated with each row or column of memory cells.
References Cited (Backward Citations)
US4144591A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-22 | 1986-05-24 | 1986-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-22 | 1990-05-24 | 1990-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-22 | 1994-05-24 | 1994-11-23 | $7700.00 | Window Closed / Lapsed |