Programmable sequencher having internal components which are microprocessor read/write interfacable

Claim 2

A programmable sequencer which is accessible by a host processor, the sequencer comprising: a bidirectional bus for carrying host processor compatible address, data, and control signals to and from the host processor; sequencing elements including one or more first elements for receiving control signals, second elements for generating an address in accordance with the control signals, and a third element for supplying the address; and duplicate registers, each duplicate register being connected to the bidirectional bus and to one of the second elements to enable the host processor to access contents of the second elements and avoid making predictions to determine the contents of the second elements based on the control signals.

Claim 3

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements; system interface means for providing interconnection between the programmable sequencer and a system; and a PLA block for receiving a portion of one of the microcode words and for receiving system status signals, TEST, μINT, I/O, from the system over the system interface means and for generating therefrom one or more of the control signals.

Claim 4

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements; system interface means for providing interconnection between the programmable sequencer and a system; and a PLA block for receiving a portion of one of the microcode words and for receiving system status signals, TEST, μINT, I/O, from the system over the system interface means and for generating therefrom one or more of the control signals.

Claim 5

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements.

Claim 6

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements.

Claim 7

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a plurality of sequencer diagnostic registers wherein a given sequencer diagnostic register in the plurality of sequencer diagnostic registers is connected to a given internal element in the plurality of internal elements, wherein the given sequencer diagnostic register receives a state of the given internal element, and wherein the given sequencer diagnostic register is readable by the host processor.

Claim 8

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a plurality of sequencer diagnostic registers wherein a given sequencer diagnostic register in the plurality of sequencer diagnostic registers is connected to a given internal element in the plurality of internal elements, wherein the given sequencer diagnostic register receives a state of the given internal element, and wherein the given sequencer diagnostic register is readable by the host processor.

Claim 9

The sequencer of claim 4 wherein the given internal element carries a program count state.

Claim 10

The sequencer of claim 4 wherein the given internal element carries a stack pointer state.

Claim 11

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a status register for storing a plurality of status bits, wherein each status bit in the plurality of status bits is set to a logical level indicating a status set by an internal element in the plurality of internal elements, wherein the plurality of status bits are readable from the status register by the host processor, and wherein a status bit in the plurality of status bits includes one of a group consisting of: a HALT bit indicating the sequencing means has stopped sequencing in response to the sequencing means processing a halt instruction; a BREAK bit indicating the sequencing means has stopped sequencing in response to having reached a breakpoint; or a SEQ -- INT bit indicating the sequencing means has processed an interrupt.

Claim 12

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a status register for storing a plurality of status bits, wherein each status bit in the plurality of status bits is set to a logical level indicating a status set by an internal element in the plurality of internal elements, wherein the plurality of status bits are readable from the status register by the host processor, and wherein a status bit in the plurality of status bits includes one of a group consisting of: a HALT bit indicating the sequencing means has stopped sequencing in response to the sequencing means processing a halt instruction; a BREAK bit indicating the sequencing means has stopped sequencing in response to having reached a breakpoint; or a SEQ -- INT bit indicating the sequencing means has processed an interrupt.

Claim 13

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a plurality of user interface registers for storing information received from either the host processor or the sequencing means; and a write flag register for storing a plurality of flag bits, wherein a given flag bit in the plurality of flag bits is associated with a given user interface register in the plurality of user interface registers and wherein the given flag bit is set to a logical level indicating whether the given user interface register was recently written to by either the host processor or the sequencing means.

Claim 14

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, wherein the plurality of registers comprise: a plurality of user interface registers for storing information received from either the host processor or the sequencing means; and a write flag register for storing a plurality of flag bits, wherein a given flag bit in the plurality of flag bits is associated with a given user interface register in the plurality of user interface registers and wherein the given flag bit is set to a logical level indicating whether the given user interface register was recently written to by either the host processor or the sequencing means.

Claim 15

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, a writable control store having an input connected to the sequencing means for storing microcode words, wherein at least one of the microcode words comprises data provided from the host, wherein the writable control store supplies a particular one of the microcode words upon receipt of the address from the sequencing means, and wherein the register further comprises a second plurality of registers which are connected to the bidirectional interconnect bus and to the writable control store to enable the host processor to write to the writable control store.

Claim 16

A host-accessible programmable sequencer comprising: a bidirectional bus for carrying host compatible address, data, and control signals to and from a host processor; sequencing means comprising a plurality of internal elements, the sequencing means for receiving control signals and supplying an address in accordance with the control signals; and a register comprising a plurality of registers which each are connected to the bidirectional bus and to one of the plurality of internal elements, other than the internal element supplying the address and other than the internal elements to which the control signals are supplied, to enable the host processor to access contents of the plurality of internal elements, a writable control store having an input connected to the sequencing means for storing microcode words, wherein at least one of the microcode words comprises data provided from the host, wherein the writable control store supplies a particular one of the microcode words upon receipt of the address from the sequencing means, and wherein the register further comprises a second plurality of registers which are connected to the bidirectional interconnect bus and to the writable control store to enable the host processor to write to the writable control store.

Claim 17

The sequencer of claim 9 further comprising: a pipeline register connected to the writable control store for receiving the particular microcode work selected from the writable control store and supplying a portion of the particular microcode word to a system.

Claim 18

The sequencer of claim 9 wherein the sequencer is fabricated on a single monolithic integrated circuit.