Patent EP0140981A1 successfully refreshed from Google Patents.
US4967346A
Expired / Lapsed
US
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Universal microprocessor interface circuit
Assignee: Advanced Micro Devices Inc
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Filing: 1988-03-14
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Granted: 1990-10-30
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Expires: 2008-03-14
Abstract
Abstract A single-chip microprogrammable sequencer (10) provides a bus (12) for connection of an external microprocessor. The sequencer includes a register file (40) which consists of a number of registers accessible to the microprocessor by which the microprocessor can monitor and control operation of the sequencer. The sequencer also includes a writeable control store (52) which is accessible to the microprocessor. Microinstructions may be written to the store by the microprocessor so that selected programs or program segments will be executed by the sequencer. A breakpoint register (104), included in the register file, is used in conjunction with a program counter portion of the sequencer providing a breakpoint facility for the microprocessor. Similarly, start, halt, reset and single-step operations may be performed by the sequencer under control of the microprocessor.
Inventors
- 👤 Philip Freidin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:10
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G05; G05B; G05B2219/00; G05B2219/20; G05B2219/22; G05B2219/2207
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
250 words
An apparatus for alternatively connecting to at least one first type of microprocessor that generates first and second timing signals of a first type or to at least one second type of microprocessor that generates first and second timing signals of a second type and for producing WRITE data signals and READ data signals in response to either the first type or the second type first and second timing signals, whereing the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type fo microprocessor and the first and second timing signals of the second type determine whether a read operation of a write operation is to occur for the at least one second microprocessor, the apparatus comprising: first means, responsive to the first and second timing signals of the first type, for producing the WRITE data signals and the READ data signals; second means, responsive to the first and second timing signals of the second type, for producing the write data signals and the READ data signals; indicating means, responsive to the first and the second timing signals of the first type or to the first and the second timing signals of the second type, for indicating whether the first and second timing signals are of the first type or of the second type; and activating means, responsive to said indicating means, for activating either said first means or said second means.
Claim 2
Independent Claim
250 words
An apparatus for alternatively connecting to at least one first type of microprocessor that generates first and second timing signals of a first type or to at least one second type of microprocessor that generates first and second timing signals of a second type and for producing WRITE data signals and READ data signals in response to either the first type or the second type first and second timing signals, whereing the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type fo microprocessor and the first and second timing signals of the second type determine whether a read operation of a write operation is to occur for the at least one second microprocessor, the apparatus comprising: first means, responsive to the first and second timing signals of the first type, for producing the WRITE data signals and the READ data signals; second means, responsive to the first and second timing signals of the second type, for producing the write data signals and the READ data signals; indicating means, responsive to the first and the second timing signals of the first type or to the first and the second timing signals of the second type, for indicating whether the first and second timing signals are of the first type or of the second type; and activating means, responsive to said indicating means, for activating either said first means or said second means.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 wherein said first means and said second means share at least one logic gate in common.
Claim 4
Dependent Claim
53 words
The apparatus of claim 1 wherein said means for activating activates said first means in response to an indication that the first and second timing signals are of the first type and activates said second means in response to an indication that the first and second timing signals are of the second type.
Claim 5
Dependent Claim
27 words
The apparatus of claim 1 wherein said means for activating includes storage means for storing signals that can activate either said first means or said second means.
Claim 6
Dependent Claim
33 words
The apparatus of claim 1, wherein said means for activating includes at least one flip-flop that can switch between a first state and a second state in response to said means for indicating.
Claim 7
Dependent Claim
60 words
The apparatus of claim 1, wherein: said means for indicating provides an indication signal that indicates whether the first and second timing signals are of the first type or of the second type; and said means for activating includes at least one flip-flop that can switch between a first state and a second state in response to the indication signal.
Claim 8
Dependent Claim
32 words
The apparatus of claim 1, wherein said second timing signal of the first type and said second timing signal of the second type share one gate to generate said READ data signals.
Claim 9
Independent Claim
309 words
An apparatus for alternatively connecting to at least one first type of microprocessor that generates first and second timing signals of a first type or to at least one second type of microprocesor that generates first and second timing signals of a second type and for producing WRITE data signals and READ data signals in response to either the first type or the second type of first and second timing signals, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second microprocessor, the apparatus comprising: first means, responsive to the first and second timing signals of the first type, for producing the WRITE data signals and the READ data signals; second means, responsive to the first and second timing signals of the second type, for producing the WRITE data signals and the READ data signals; indicating means, responsive to the first and the second timing signals of the first type or to the first and the second timing signals of the second type, for indicating whether the first and second timing signals are of the first type or of the second type; and activating means including at least one flip-flop that can switch between a first state and a second state in response to said indicating means; wherein said first means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the first state; and wherein said second means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the second state.
Claim 10
Independent Claim
309 words
An apparatus for alternatively connecting to at least one first type of microprocessor that generates first and second timing signals of a first type or to at least one second type of microprocesor that generates first and second timing signals of a second type and for producing WRITE data signals and READ data signals in response to either the first type or the second type of first and second timing signals, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second microprocessor, the apparatus comprising: first means, responsive to the first and second timing signals of the first type, for producing the WRITE data signals and the READ data signals; second means, responsive to the first and second timing signals of the second type, for producing the WRITE data signals and the READ data signals; indicating means, responsive to the first and the second timing signals of the first type or to the first and the second timing signals of the second type, for indicating whether the first and second timing signals are of the first type or of the second type; and activating means including at least one flip-flop that can switch between a first state and a second state in response to said indicating means; wherein said first means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the first state; and wherein said second means produces the WRITE data signals and the READ data signals when said at least one flip-flop is in the second state.
Claim 11
Independent Claim
315 words
A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determined whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of: providing at least one logic signal in a first logical state; generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals of the second type; performing either a step of maintaining the state of the at least one logical signal in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the at least one logic signal to a second logical state in response to the receipt of first and second timing signals of the second type, according to the indicating signal; alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type; producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the at least one logic signal is in the first logical state; and producing the WRITE data signal and the READ data signals from received signals using second means for producing when the at least one logic signal is in the second logical state.
Claim 12
Independent Claim
315 words
A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determined whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of: providing at least one logic signal in a first logical state; generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals of the second type; performing either a step of maintaining the state of the at least one logical signal in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the at least one logic signal to a second logical state in response to the receipt of first and second timing signals of the second type, according to the indicating signal; alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type; producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the at least one logic signal is in the first logical state; and producing the WRITE data signal and the READ data signals from received signals using second means for producing when the at least one logic signal is in the second logical state.
Claim 13
Independent Claim
298 words
A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of: providing a flip-flop in a first logical state; generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals to the second type; performing either a step of maintaining the state of the flip-flop in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the flip-flop to a second logical state in response to the receipt of initial first and second timing signals of the second type, according to the indicating signal; alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type; producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the flip-flop is in the first logical state; and producing the WRITE date signals and the READ data signals from the received signals using second means for producing when the flip-flop is in the second logical state.
Claim 14
Independent Claim
298 words
A method for producing WRITE data signals and READ data signals in response to either first and second timing signals of a first type generated by a first type of microprocessor or in response to first and second timing signals of a second type generated by a second type of microprocessor, wherein the first and second timing signals of the first type determine whether a read operation or a write operation is to occur for the at least one first type of microprocessor and the first and second timing signals of the second type determine whether a read operation or a write operation is to occur for the at least one second mircoprocessor, the method comprising the steps of: providing a flip-flop in a first logical state; generating an indicating signal in response to first and second timing signals of the first type or first and second timing signals to the second type; performing either a step of maintaining the state of the flip-flop in the first logical state in response to the receipt of first and second timing signals of the first type or a step of changing the state of the flip-flop to a second logical state in response to the receipt of initial first and second timing signals of the second type, according to the indicating signal; alternatively receiving first and second timing signals of the first type or first and second timing signals of the second type; producing the WRITE data signals and the READ data signals from the received signals using first means for producing when the flip-flop is in the first logical state; and producing the WRITE date signals and the READ data signals from the received signals using second means for producing when the flip-flop is in the second logical state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-29 | 1994-04-30 | 1994-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-29 | 1998-04-30 | 1998-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-29 | 2002-04-30 | 2002-10-30 | $7700.00 | Window Closed / Lapsed |