US5179716A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable expandable controller with flexible I/O
Assignee: Lattice Semiconductor Corp
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Filing: 1989-06-21
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Granted: 1993-01-12
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Expires: 2009-06-21
Abstract
Abstract A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.
Inventors
- 👤 Om P. Agrawal
- 👤 Arthur H. Khu
- 👤 William Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/223
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
143 words
A programmable controller comprising: microaddress control logic means for receiving sequencing signals and including program counter means to develop a program count address from said sequencing signals; memory means coupled to said microaddress control logic, said memory means including a plurality of microinstruction word storage locations and being operative to output a microinstruction word after receiving said program count address, wherein said microinstruction word has an internal field and a control field; a microinstruction decoder having inputs coupled to said memory means and having outputs coupled to said microaddress control logic, said microinstruction decoder receiving said internal field and operative to develop said sequencing signals; and an output buffer having inputs coupled to both said memory means and said microaddress control logic means, said output buffer receiving both said control field and said program count address and operative to develop output signals therefrom.
Claim 2
Dependent Claim
143 words
A programmable controller comprising: microaddress control logic means for receiving sequencing signals and including program counter means to develop a program count address from said sequencing signals; memory means coupled to said microaddress control logic, said memory means including a plurality of microinstruction word storage locations and being operative to output a microinstruction word after receiving said program count address, wherein said microinstruction word has an internal field and a control field; a microinstruction decoder having inputs coupled to said memory means and having outputs coupled to said microaddress control logic, said microinstruction decoder receiving said internal field and operative to develop said sequencing signals; and an output buffer having inputs coupled to both said memory means and said microaddress control logic means, said output buffer receiving both said control field and said program count address and operative to develop output signals therefrom.
Claim 3
Dependent Claim
36 words
A programmable controller as recited in claim 1 further comprising test means for receiving a plurality of test inputs and operative to develop a test output therefrom, wherein said microinstruction decoder further receives said test output.
Claim 4
Dependent Claim
18 words
A programmable controller as recited in claim 2 wherein said test means further comprises a programmable test buffer.
Claim 5
Dependent Claim
35 words
A programmable controller as recited in claim 3 wherein said test buffer includes a test register for storing asynchronous test signals and selectively synchronizing said asynchronous test signals with clock signals internal to said controller.
Claim 6
Dependent Claim
25 words
A programmable controller as recited in claim 3 wherein said test buffer includes programmable input register means which can be programmed as registered or transparent.
Claim 7
Dependent Claim
46 words
A programmable controller as recited in claim 5 wherein said programmable test register means includes, for each test input, a programmable register for receiving the corresponding test input, and wherein each programmable register can be programmed as registered or transparent independently from the other programmable registers.
Claim 8
Dependent Claim
77 words
A programmable controller as recited in claim 2 wherein said microaddress logic means further includes loop counter means for developing a loop count, and wherein said microaddress control logic means further includes branch control means for developing branch control inputs to both said program counter means and said loop counter means, said branch control means receiving said internal field and said test inputs and developing said branch control inputs from said internal field and said test inputs.
Claim 9
Dependent Claim
33 words
A programmable controller as recited in claim 7 further comprising mask storage means to store a mask derived from said internal field, said mask storage means being coupled to said branch control means.
Claim 10
Dependent Claim
33 words
A programmable controller as recited in claim 8 further comprising constant storage means to store a constant derived from said internal field, said constant storage means being coupled to said branch control means.
Claim 11
Dependent Claim
70 words
A programmable controller as recited in claim 9 further comprising a flag, wherein said branch control means comprises means for comparing said constant with said test inputs under said mask and for setting said flag if said constant equals said test inputs under said mask; and wherein said test means receives a value of said flag, and said test means is enabled to provide said value as said test output.
Claim 12
Dependent Claim
33 words
A programmable controller as recited in claim 7 further comprising constant storage means to store a constant derived from said internal field, said constant storage means being coupled to said branch control means.
Claim 13
Dependent Claim
32 words
A programmable controller as recited in claim 7 wherein said microaddress logic means further includes stack means interactive with at least one of said program counter means and said loop counter means.
Claim 14
Dependent Claim
70 words
A programmable controller as recited in claim 2 wherein: said test means is operative to receive one or more condition signals; and said test means is operative to develop said test output so that: when said test inputs are a first predetermined value, said test output depends on said condition signals; and when said test inputs are a second predetermined value, said test output is independent from said condition signals.
Claim 15
Dependent Claim
24 words
An integrated circuit comprising: the programmable controller of claim 2; and a plurality of pins, each pin for receiving one of said test inputs.
Claim 16
Dependent Claim
34 words
A programmable controller as recited in claim 1 wherein said output buffer includes output multiplexer means for multiplexing said control field and said program count address to an output bus of said output buffer.
Claim 17
Dependent Claim
24 words
An integrated circuit comprising: the programmable controller of claim 15; and one or more pins connected to the output bus of said output buffer.
Claim 18
Dependent Claim
23 words
A controller comprising: the integrated circuit of claim 16; and one or more memory devices of which has inputs coupled to said pins.
Claim 19
Dependent Claim
45 words
A programmable controller as recited in claim 1 wherein said microaddress logic means further includes loop counter means to develop a loop count, and wherein said output buffer includes output multiplexer means for receiving said control field, said program count address, and said loop count.
Claim 20
Dependent Claim
24 words
A programmable controller as recited in claim 18 wherein said output multiplexer means further receives a multiplexer control signal developed by said microinstruction decoder.
Claim 21
Dependent Claim
60 words
A programmable controller as recited in claim 19 wherein said control field has an upper control subfield and a lower control subfield, wherein aid upper control subfield is multiplexed with one of said program count address and said loop count, and wherein said lower control subfield is multiplexed with the other of said program count address and said loop count.
Claim 22
Dependent Claim
24 words
An integrated circuit comprising: the programmable controller of claim 19; and one or more pins for providing output signals from said output multiplexer means.
Claim 23
Dependent Claim
46 words
A programmable controller as recited in claim 1 wherein said memory means includes programmable, read-only memory having an address input for receiving said program count address and having a data output, and wherein said memory means further includes latching pipeline means for receiving said data output.
Claim 24
Dependent Claim
45 words
A programmable controller as recited in claim 1 wherein said memory means includes read/write memory having an address input for receiving said program count address and having a data output, and wherein said memory means further includes latching pipeline means for receiving said data output.
Claim 25
Dependent Claim
20 words
A programmable controller as recited in claim 23 further comprising writing means for loading microinstruction words into said read/write memory.
Claim 26
Dependent Claim
30 words
A programmable controller as recited in claim 24 wherein said writing means includes serial shift register means for receiving a serial input data and operative t load said microinstruction words.
Claim 27
Dependent Claim
45 words
A programmable controller as recited in claim 25 wherein said serial shift register means includes a first serial shift register to hold a microinstruction word address, and a second serial shift register to hold a microinstruction word to be stored at said microinstruction word address.
Claim 28
Dependent Claim
29 words
An integrated circuit comprising: the programmable controller of claim 1; and one or more pins connected to said output buffer, for providing said output signals from said output buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |