Single-chip programmable controllers

Claim 2

An integrated programmable controller on a single integrated circuit chip comprising: a programmable microprogram memory, said memory having an address input and an output for microinstruction words stored in such memory, each of which microinstruction words includes an internal microinstruction field for said controller and a user-defined general purpose external output field for said controller, wherein said internal microinstruction field includes an internal opcode subfield and an internal immediate data/masking subfield; microaddress control logic, including a control logic multiplexer having a plurality of inputs and having an output coupled to the address input of said programmable microprogram memory, said control logic multiplexer having a first one of its plurality of inputs logically coupled to an external data input terminal of said programmable controller, said microaddress control logic receiving the internal immediate data/masking subfield of the microinstruction field; and microinstruction decoder means, having an opcode input coupled to and receiving the opcode subfield of the microinstruction word output of the programmable microprogram memory, said microinstruction decode means decoding instructions provided by the opcode subfield, said microinstruction decode means having a plurality of control outputs internally coupled to the microaddress control logic for controlling the operation thereof.

Claim 3

The controller of claim 1 wherein the programmable microprogram memory is a fuse-programmable memory.

Claim 4

The controller of claim 1 wherein the programmable microprogram memory includes a pipeline register internally coupled in series with the output for the microinstruction words stored in said memory.

Claim 5

The controller of claim 3 wherein the internal microinstruction field of a memory microinstruction word includes an output-enable bit and wherein the pipeline register includes means for internally enabling at least one predetermined bit of the user-defined general purpose output control field which means for enabling is activated by said output-enable bit of said internal microinstruction field to externally provide at least one predetermined bit of the user-defined general purpose output control field.

Claim 6

The controller of claim 1 wherein said microaddress control logic includes GOTO logic having a GOTO output, which output is coupled to said first one of the plurality of inputs of the control logic multiplexer, said GOTO logic logically coupling the external data input to said first one of the plurality of inputs of the control logic multiplexer; said GOTO logic having an immediate-data/masking input coupled to the internal immediate-data/masking subfield of the microinstruction field; wherein said GOTO logic includes means for selecting the internal immediate data/masking subfield and the external data input to be provided at the output of said GOTO logic; and wherein said GOTO logic includes means for bitwise masking the external data input with the internal immediate data/masking subfield to provide a masked version of the external data field at the output of the GOTO logic.

Claim 7

The controller of claim 5 wherein said internal microinstruction field includes an internal constant subfield; and wherein said GOTO logic includes comparison logic means, having an input coupled to the internal constant subfield, said comparison logic means having an input coupled to the GOTO output, and said comparison logic means having an equal-to output at which is present an equal-to (EQ) signal when the masked version of the external data field is equal to the internal constant subfield.

Claim 8

The controller of claim 6 wherein said microinstruction word includes an internal test condition select subfield, said controller including: a condition code selection logic having an output coupled to a condition code input of the microinstruction decoder means; said condition code selection logic having an input coupled to the internal test condition select subfield of a microinstruction word; said condition code selection logic having an external test data input coupled to the external data input of said GOTO logic such that both the external test data input and the external data input of said GOTO logic share a common input to the integrated circuit chip with said condition code selection logic being controlled by the internal test condition select subfield of a microinstruction word to select an provide at its output a selected bit of the external test data input.

Claim 9

The controller of claim 7 wherein said controller includes said condition code selection logic having a condition code CC input and said condition code selection logic having an equal-to input coupled to the equal-to output of the comparison logic of the GOTO logic; and said condition code selection logic being controlled by the internal test condition select subfield of a microinstruction word to select and provide at its output a selected one of the external test data, the condition code CC, and the equal-to inputs.

Claim 10

The controller of claim 1 wherein the microaddress control logic includes a reconfigureable loop counter/subroutine register arrangement comprising: a loop counter having an input and an output; a loop counter input multiplexer having an output coupled to the input of said loop counter, said loop counter input multiplexer having a first input logically coupled to the external data input termianl and also coupled to said first one of the inputs of the control logic multiplexer, said loop counter input multiplexer having a second inut coupled to the output of a means for decrementing the count of the loop counter output, said loop counter input multiplexer having a third input coupled to the output of said loop counter and to an input of said means for decrementing the count of said loop counter; a subroutine register having a data input and an output, which is coupled to a fourth input to said loop counter input multiplexer and which is coupled to an input of the control logic multiplexer; a subroutine register input multiplexer having an output coupled to the data input of the subroutine register, said subroutine register input multiplexer having an input coupled to the loop counter output, said subroutine register input multiplexer having another input coupled to the output of the subroutine register; and said subroutine register input multiplexer and said loop counter input multiplexer being controlled by some of the plurality of control outputs from the microinstruction decoder means to configure the loop counter/subroutine register in a number of operational arrangements including a separate stack register, a separate counter, a two-deep stack register, and a two-deep nested counter.

Claim 11

The controller of claim 9 wherein said microaddress control logic includes a program counter (PC) having an address input coupled to the output of the control logic multiplexer, said program counter having an output coupled to a program count input of the control logic multiplexer; incrementing means for providing an incremented value of the program counter, said incrementing means having an input coupled to the output of the program counter, said incrementing means having an output coupled to an incremented program count input of the control logic multiplexer, and said incrementing means having an output coupled to an incremented-program-count input of the subroutine register input multiplexer.

Claim 12

An integrated-circuit programmable controller on a single integrated-circuit chip, comprising: (1) a programmable microprogram memory, said memory having an address input bus and a memory output bus for microinstruction words stored at locations in said memory, wherein each of said microinstruction words includes an internal microinstruction field and an external user-defined general purpose output control field provided on respective lines of said memory output bus, wherein said internal microinstruction field includes an opcode subfield and an immediate data/mask subfield; (2) microaddress control logic including: (a) a program control multiplexer having a plurality of input buses and an output bus which is coupled to the address input bus of said microprogram memory; (b) a loop counter having an input bus and an output bus; (c) a program counter having an input bus coupled to the output bus of the program control multiplexer, and having an output bus coupled to a first one of said plurality of program control multiplexer input buses; (d) a subroutine stack register having an input bus coupled to the output bus of said program counter and having an output bus coupled to a second one of said plurality of program control multiplexer input buses; and (e) GOTO logic having a GOTO output, which output is coupled to a GOTO input of the plurality of control logic multiplexer inputs, said GOTO logic having an immediate data/masking input coupled to the immediate data/masking subfield of the microinstruction field, said GOTO logic having an external data input, wherein said GOTO logic includes means for selecting and providing the immediate data/masking subfield and the external data input at the output of said GOTO logic and wherein said GOTO logic includes means for bitwise masking the external data input with the immediate data/masking subfield to providing a masked external data field at the output of the GOTO logic; (3) microinstruction decoder means having an opcode input coupled to the opcode subfield of the microinstruction word output of the programmable microprogram memory, said microinstruction decoder means having a plurality of control outputs coupled to the microaddress control logic for controlling operation of the program control multiplexer, the loop counter, the subroutine stack register, and the GOTO logic.

Claim 13

An integrated-circuit programmable controller on a single integrated-circuit chip, comprising: (1) a programmable microprogram memory, said memory having an address input bus and a memory output bus for microinstruction words stored at locations in said memory, wherein each of said microinstruction words includes an internal microinstruction field and an external user-defined general purpose output control field provided on respective lines of said memory output bus, wherein said internal microinstruction field includes an opcode subfield and an immediate data/mask subfield; (2) microaddress control logic including: (a) a program control multiplexer having a plurality of input buses and an output bus which is coupled to the address input bus of said microprogram memory; (b) a loop counter having an input bus and an output bus; (c) a program counter having an input bus coupled to the output bus of the program control multiplexer, and having an output bus coupled to a first one of said plurality of program control multiplexer input buses; (d) a subroutine stack register having an input bus coupled to the output bus of said program counter and having an output bus coupled to a second one of said plurality of program control multiplexer input buses; and (e) GOTO logic having a GOTO output, which output is coupled to a GOTO input of the plurality of control logic multiplexer inputs, said GOTO logic having an immediate data/masking input coupled to the immediate data/masking subfield of the microinstruction field, said GOTO logic having an external data input, wherein said GOTO logic includes means for selecting and providing the immediate data/masking subfield and the external data input at the output of said GOTO logic and wherein said GOTO logic includes means for bitwise masking the external data input with the immediate data/masking subfield to providing a masked external data field at the output of the GOTO logic; (3) microinstruction decoder means having an opcode input coupled to the opcode subfield of the microinstruction word output of the programmable microprogram memory, said microinstruction decoder means having a plurality of control outputs coupled to the microaddress control logic for controlling operation of the program control multiplexer, the loop counter, the subroutine stack register, and the GOTO logic.