Processor unit for microcomputer systems

Claim 2

In a microcomputer system, including memory means for storing a plurality of multi-bit instruction words and sequencer means coupled to said memory means for controlling the sequence of instructions accessed from said memory means, a processor device coupled to said memory means and responsive to said instruction words for receiving and processing data words, the processor device comprising: decoder means for receiving said instruction words and for generating therefrom a plurality of control signals; storage means for temporarily storing said data words, said storage means including at least a first and a second memory element; arithmetic-logic means having first, second, and third operand inputs operably coupled to said storage means for receiving said stored data words at said operand inputs and selectively performing arithmetic and logic operations thereon in response to said control signals; combinatorial logic means interconnecting said storage means and only said third operand input for receiving and shifting stored data words; and first multiplex means for selectively communicating said first and second memory elements to said first and second operand inputs and to said combinatorial logic means.

Claim 3

The processor device of claim 1, wherein the combinatorial logic means includes means for circular shifting said received stored data words.

Claim 4

The processor device of claim 1, further comprising priority encoding means for selectively receiving a selected one of said stored data words and issuing a prioritization word indicative of the bit position of the highest order ONE contained in said selected data word in a single clock cycle.

Claim 5

The processor device of claim 3, wherein said arithmetic-logic means is capable of masking selected bits of said selected data word, said priority encoding means receiving the unselected bits of said selected data word from said arithmetic-logic means so that said priority encoding means issues a prioritization word indicative of the bit position of the highest ONE contained in the unselected bits in said selected data word.

Claim 6

The processor device of claim 1, further comprising input means for receiving and communicating instruction words to said first multiplex means said first multiplex means including further means for selectively communicating said input means to said first and second operand inputs and to said combinatorial logic means.

Claim 7

The processor device of claim 1, wherein said instruction words are 16-bits, and wherein said decoder means includes means for selectively processing 16-bit data words in response to a predetermined one bit of said instruction being set to a first state and for processing 8-bit data words in response to said predetermined bit being set to a second state.

Claim 8

The processor device of claim 1 wherein said arithmetic-logic means performs arithmetic and logic operations in a single clock cycle.

Claim 9

The processor device of claim 1 further comprising: register means coupled to said arithmetic-logic means for temporarily storing signals indicative of the status of operations of said arithmetic-logic means; and second multiplex means for selectively coupling said arithmetic-logic means output and said register means to said storage means.

Claim 10

In a microprocessor system, including memory means for storing a plurality of multi-bit instruction words and sequencer means coupled to said memory means for controlling the sequence of instructions accessed from said memory means, a processor device coupled to said memory means and responsive to said instruction words for receiving and processing data words, the processor device comprising: decoder means for receiving said instruction words and for generating therefrom a plurality of control signals; storage means for temporarily storing said data words, said storage means having first and second memory elements; arithmetic-logic means having first, second and third operand inputs operably coupled to said storage means for receiving said stored data words at said operand inputs and selectively performing in a single clock cycle arithmetic and logic operations thereon in response to said control signals, wherein in a three-operand input operation performance, said third operand operates on both said first and second operands; combinatorial means interconnecting said storage means and only said third operand input for receiving and shifting said stored data words, said combinatorial logic means further including means for circular shifting said received stored data words; and multiplex means for selectively communicating said first and second memory elements to said first and second operand inputs and to said combinatorial logic means.

Claim 11

In a microprocessor system, including memory means for storing a plurality of multi-bit instruction words and sequencer means coupled to said memory means for controlling the sequence of instructions accessed from said memory means, a processor device coupled to said memory means and responsive to said instruction words for receiving and processing data words, the processor device comprising: decoder means for receiving said instruction words and for generating therefrom a plurality of control signals; storage means for temporarily storing said data words, said storage means having first and second memory elements; arithmetic-logic means having first, second and third operand inputs operably coupled to said storage means for receiving said stored data words at said operand inputs and selectively performing in a single clock cycle arithmetic and logic operations thereon in response to said control signals, wherein in a three-operand input operation performance, said third operand operates on both said first and second operands; combinatorial means interconnecting said storage means and only said third operand input for receiving and shifting said stored data words, said combinatorial logic means further including means for circular shifting said received stored data words; and multiplex means for selectively communicating said first and second memory elements to said first and second operand inputs and to said combinatorial logic means.

Claim 12

The processor device of claim 9 further comprising: input means for receiving and communicating instruction words to said multiplex means, said multiplex means having further means for selectively communicating said input means to said first and second operand inputs and to said combinatorial logic means.

Claim 13

The processor device of claim 9, further comprising priority encoding means for selectively receiving a selected one of said stored data words and issuing a priorization word indicative of the bit position of the highest order ONE contained in said selected data word in a single clock cycle.

Claim 14

In a microprocessor system, including memory means for storing a plurality of multi-bit instruction words and sequencer means coupled to said memory means for controlling the sequence of instructions accessed from said memory means, a processor device coupled to said memory means and responsive to said instruction words for receiving and processing data words, the processor device comprising: decoder means for receiving said instruction words and for generating therefrom a plurality of control signals; arithmetic-logic means having first, second and third operand inputs for receiving said data words at said operand inputs and selectively performing arithmetic and logic operations thereon in response to said control signals, said arithmetic and logic operations results appearing at an output; a RAM, coupled to said arithmetic-logic means operand inputs and output, for holding said data words to and from said arithmetic-logic means; an accumulator register, coupled to said arithmetic-logic means operand inputs and output, for holding said data words to and from said arithmetic-logic means; a data storage latch, coupled to said arithmetic-logic means operand inputs and output, for holding data words to and from said arithmetic-logic means, said data storage latch further coupled to a data bus for holding data said words from said data bus; combinatorial logic means connected to said third operand input only; and multiplex means for selectively coupling said RAM and said accumulator register to said first and second operand inputs and to said combinatorial logic means.

Claim 15

In a microprocessor system, including memory means for storing a plurality of multi-bit instruction words and sequencer means coupled to said memory means for controlling the sequence of instructions accessed from said memory means, a processor device coupled to said memory means and responsive to said instruction words for receiving and processing data words, the processor device comprising: decoder means for receiving said instruction words and for generating therefrom a plurality of control signals; arithmetic-logic means having first, second and third operand inputs for receiving said data words at said operand inputs and selectively performing arithmetic and logic operations thereon in response to said control signals, said arithmetic and logic operations results appearing at an output; a RAM, coupled to said arithmetic-logic means operand inputs and output, for holding said data words to and from said arithmetic-logic means; an accumulator register, coupled to said arithmetic-logic means operand inputs and output, for holding said data words to and from said arithmetic-logic means; a data storage latch, coupled to said arithmetic-logic means operand inputs and output, for holding data words to and from said arithmetic-logic means, said data storage latch further coupled to a data bus for holding data said words from said data bus; combinatorial logic means connected to said third operand input only; and multiplex means for selectively coupling said RAM and said accumulator register to said first and second operand inputs and to said combinatorial logic means.

Claim 16

The processor device of claim 12 wherein memory locations in said RAM for said data words are identified by address signals in said instruction words.

Claim 17

The process device of claim 13 wherein said multiplex means comprises: first multiplex means for selectively coupling said RAM, said accumulator register and said data storage latch to said first operand input of said arithmetic-logic means responsive to said control signals; second multiplex means for selectively coupling said RAM and said accumulator register to said second operand input of said arithmetic-logic means responsive to said control signals; and third multiplex means for selectively coupling said RAM, said accumulator register, and said data storage latch to said third operand input of said arithmetic-logic means through said combinatorial logic means responsive to said control signals.

Claim 18

The processor device of claim 14 wherein said second multiplex means also receives instruction words for selectively communicating said instruction words to said second operand input responsive to said control signals.