US5018091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Discrete fourier transform calculating processor comprising a real-time testing device
Assignee: Thales SA
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Filing: 1989-06-23
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Granted: 1991-05-21
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Expires: 2009-06-23
Abstract
Abstract The invention pertains mainly to a processor for the calculation of the discrete Fourier transform, comprising a real-time testing device. The device according to the invention uses the theorem of Parseval to ascertain that the processor is working properly. The device according to the invention uses, for example, an adder and a multiplier to calculate either the discrete Fourier transform or the members of the equation. Thus, by using temporal redundancy, the complexity, area and price of the processor are reduced. The invention is applied mainly to the calculation of spectra.
Inventors
- 👤 Arnaud du Chene
- 👤 Bernard Dias
- 👤 Gerard Bergeon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:30
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1637; G06F11/1654; G06F17/00; G06F17/10; G06F17/14; G06F17/141
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
264 words
A device for calculating a discrete Fourier transform and for conducting a comparison according to Parseval's equation comprising: input buffer memory means for receiving input data; multiplication means connected to said buffer memory means; addition means and second buffer memory means interconnected with said multiplication means for performing the operations necessary to calculate the various terms of said discrete Fourier transform; output buffer memory means for transmitting said calculated terms; memory means for storing and delivering said input data and said calculated terms; and controlling means for controlling the operation of said input buffer memory means, said multiplication means, said addition means and said second buffer memory means, said output buffer memory means, and said memory means; first switching means connected between said input buffer memory means and said multiplication means and controlled by said controlling means for allowing said multiplication means to square said input data during a testing operation according to Parseval's equation; second switching means connected to an output of said addition means and alternatively for connecting an input of said addition means to said output of said addition means to form an accumulator and connecting to said second buffer memory means; subtracter means for subtracting a left side from a right side of Parseval's equation as calculated by said multiplication means and addition means when they are connected by said first and second switching means for the testing operation; and comparison means for comparing an absolute value of the difference between the right side and the left side of Parseval's equation provided by said subtracting means and a tolerance value.
Claim 2
Independent Claim
264 words
A device for calculating a discrete Fourier transform and for conducting a comparison according to Parseval's equation comprising: input buffer memory means for receiving input data; multiplication means connected to said buffer memory means; addition means and second buffer memory means interconnected with said multiplication means for performing the operations necessary to calculate the various terms of said discrete Fourier transform; output buffer memory means for transmitting said calculated terms; memory means for storing and delivering said input data and said calculated terms; and controlling means for controlling the operation of said input buffer memory means, said multiplication means, said addition means and said second buffer memory means, said output buffer memory means, and said memory means; first switching means connected between said input buffer memory means and said multiplication means and controlled by said controlling means for allowing said multiplication means to square said input data during a testing operation according to Parseval's equation; second switching means connected to an output of said addition means and alternatively for connecting an input of said addition means to said output of said addition means to form an accumulator and connecting to said second buffer memory means; subtracter means for subtracting a left side from a right side of Parseval's equation as calculated by said multiplication means and addition means when they are connected by said first and second switching means for the testing operation; and comparison means for comparing an absolute value of the difference between the right side and the left side of Parseval's equation provided by said subtracting means and a tolerance value.
Claim 3
Dependent Claim
19 words
A device according to claim 1 wherein said addition means comprises an accumulating adder connected to said multiplication means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |