US4630194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for expediting sub-unit and memory communications in a microprocessor implemented data processing system having a multibyte system bus that utilizes a bus command byte
Assignee: International Business Machines Corp
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Filing: 1983-06-02
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Granted: 1986-12-16
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Expires: 2003-06-02
Abstract
Abstract Bus command generation apparatus is provided for a microprocessor implemented data processing system that uses a multibyte width system bus requiring a bus command byte since a complete bus command byte is ordinarily unavailable directly from a microprocessor. A bus command register is loaded with a preliminary bus command, certain bits of which are then modified in accordance with the operation to be performed. The limited command information available from the microprocessor that controls I/O operations is utilized to modify the preliminary bus command bytes without any need to access memory for bus command information. The bus command generation apparatus is adapted to pass a preliminary bus command byte unaltered, under predefined conditions, to the system bus.
Inventors
- 👤 Burton L. Oliver
- 👤 David C. Preston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:28
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
296 words
Apparatus for generating a system bus command byte from a processing unit of a microprocessor implemented data processing system in response to a set of informaion, said set of information including a set of preliminary bus command bytes having predetermined command significant bits and a set control information, said control information being supplied by said microprocessor and said bus command bytes being supplied by a storage means and representing clues relating to the type of operation to be performed by a mainframe computer, said microprocessing unit interfacing with a multibyte width system bus of said mainframe computer which requires said bus command byte, said microprocessor being incapable of supplying said bus command byte, said apparatus comprising: storage means for storing said set of preliminary bus command byte therein; bus command register means connected to said storage means for storing one of said set of preliminary bus command bytes therein; decoding means, connected to said microprocessor, said storage means and said bus command register means for receiving a storage address of the preliminary bus command byte to be stored in said bus command register means and for gating said preliminary bus command byte from said storage means into said bus command register means in response thereto, and logic circuit means, connected to an output of said bus command register means and said microprocessor and responsive to the preliminary bus command byte stored in said bus command register means and to said control information supplied from said microprocessor for changing at least one of the command significant bits of said preliminary bus command byte in accordance with said control information thereby developing said system bus command byte required by said multibyte width system bus, said logic circuit means placing said system bus command byte on said system bus.
Claim 2
Dependent Claim
296 words
Apparatus for generating a system bus command byte from a processing unit of a microprocessor implemented data processing system in response to a set of informaion, said set of information including a set of preliminary bus command bytes having predetermined command significant bits and a set control information, said control information being supplied by said microprocessor and said bus command bytes being supplied by a storage means and representing clues relating to the type of operation to be performed by a mainframe computer, said microprocessing unit interfacing with a multibyte width system bus of said mainframe computer which requires said bus command byte, said microprocessor being incapable of supplying said bus command byte, said apparatus comprising: storage means for storing said set of preliminary bus command byte therein; bus command register means connected to said storage means for storing one of said set of preliminary bus command bytes therein; decoding means, connected to said microprocessor, said storage means and said bus command register means for receiving a storage address of the preliminary bus command byte to be stored in said bus command register means and for gating said preliminary bus command byte from said storage means into said bus command register means in response thereto, and logic circuit means, connected to an output of said bus command register means and said microprocessor and responsive to the preliminary bus command byte stored in said bus command register means and to said control information supplied from said microprocessor for changing at least one of the command significant bits of said preliminary bus command byte in accordance with said control information thereby developing said system bus command byte required by said multibyte width system bus, said logic circuit means placing said system bus command byte on said system bus.
Claim 3
Dependent Claim
56 words
The apparatus according to claim 1, further comprising parity generating means, connected between said logic circuit means and said system bus, for generating a new parity bit in response to said preliminary bus command byte, said system bus command byte and said new parity bit being placed on said system bus by said logic circuit means.
Claim 4
Dependent Claim
68 words
The apparatus according to claim 2 wherein said logic circuit means includes circuit means, responsive to at least one predetermined bit of said preliminary bus command byte, for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus when the status of said predetermined bit indicates that no bit changes should be made to the bits of said preliminary bus command byte.
Claim 5
Dependent Claim
147 words
The apparatus according to claim 3 wherein: (a) said storage means stores therein a non-preliminary bus command information bit that indicates whether a preliminary command byte should be modified before being placed on said system bus; (b) said bus command register means is adapted to accept and store said non-preliminary bus command byte information bit therein in addition to said preliminary bus command byte; (c) said decoding means is connected to also receive the storage address of said non-preliminary bus command information bit and to gate said bit from said storage means to said bus command register means; and (d) said logic means further includes circuit means, responsive to the status of said non-preliminary command byte information bit for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus in accordance with the status of said non-preliminary bus command information bit.
Claim 6
Dependent Claim
147 words
The apparatus according to claim 2 wherein: (a) said storage means stores therein a non-preliminary bus command information bit that indicates whether a preliminary command byte should be modified before being placed on said system bus; (b) said bus command register means is adapted to accept and store said non-preliminary bus command byte information bit therein in addition to said preliminary bus command byte; (c) said decoding means is connected to also receive the storage address of said non-preliminary bus command information bit and to gate said bit from said storage means to said bus command register means; and (d) said logic means further includes circuit means, responsive to the status of said non-preliminary command byte information bit for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus in accordance with the status of said non-preliminary bus command information bit.
Claim 7
Dependent Claim
68 words
The apparatus according to claim 1 wherein said logic circuit means includes circuit means, responsive to at least one predetermined bit of said preliminary bus command byte, for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus when the status of said predetermined bit indicates that no bit changes should be made to the bits of said preliminary bus command byte.
Claim 8
Dependent Claim
147 words
The apparatus according to claim 6 wherein: (a) said storage means stores therein a non-preliminary bus command information bit that indicates whether a preliminary command byte should be modified before being placed on said system bus; (b) said bus command register means is adapted to accept and store said non-preliminary bus command byte information bit therein in addition to said preliminary bus command byte; (c) said decoding means is connected to also receive the storage address of said non-preliminary bus command information bit and to gate said bit from said storage means to said bus command register means; and (d) said logic means further includes circuit means, responsive to the status of said non-preliminary command byte information bit for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus in accordance with the status of said non-preliminary bus command information bit.
Claim 9
Dependent Claim
151 words
The apparatus according to claim 1 wherein: (a) said storage means further accommodates and stores therein a non-preliminary bus command information bit that indicates whether a preliminary command byte should be modified before being placed on said system bus; (b) said bus command register means is adapted to accept and store said non-preliminary bus command byte information bit therein in addition to said preliminary bus command byte; (c) said decoding means is connected to also receive the storage address of said non-preliminary bus command information bit and to gate said bit from said storage means to said bus command register means; and (d) said logic circuit means further includes circuit means, responsive to the status of said non-preliminary command byte information bit for passing said preliminary bus command byte unchanged through said logic circuit means to said system bus in accordance with the status of said non-preliminary bus command information bit.
References Cited (Backward Citations)
US4340933A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-15 | 1990-06-16 | 1990-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-15 | 1994-06-16 | 1994-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-15 | 1998-06-16 | 1998-12-16 | $7700.00 | Window Closed / Lapsed |