Telemetry data processor

Claim 1

A data processor for high bandwidth data, said data processor having a cylindrical architecture and comprising: means for distributing the data onto n generally parallel buses where n is any preselected positive integer greater than 3; several processor modules directly coupled to each bus, with each processor module directly coupled to two adjacent buses, where bus(r) is defined as being "adjacent" to bus(r+1) and to bus(r-1), r being any positive integer from 2 through n-1, and, in addition, bus(n) is defined as being "adjacent" to bus(1); and several memory modules directly coupled to each bus, with each memory module directly coupled to two adjacent buses; wherein each individual module has a first, relatively direct, communications relationship with each other module that is directly coupled to a bus to which said individual module is directly coupled in view of the fact that communications between such modules occur over but a single intervening bus, and a second, relatively indirect, communications relationship with each other module that is directly coupled to a bus to which said individual module is not directly coupled in view of the fact that communications between any two such modules is routed via at least one additional intermediate module and two buses; and distinct buses can simultaneously be activated to communicate distinct packets of information between different modules wherein each bus comprises data lines and address lines, and each processor module comprises: first and second ports for coupling to the two adjacent buses, respectively; an address translation/access protection unit coupled to the address lines at each of said ports; a microprocessor coupled to the address translation/access protection unit and to the data lines at each of said ports via a set of transceivers; a first local memory coupled to the address translation/access protection unit and to the data lines at each of said ports; a second local memory coupled directly to the microprocessor and coupled to the address translation/access protection unit via the set of transceivers; and a cache memory coupled directly to the microprocessor, coupled directly to the second local memory, and coupled to the address translation/access protection unit via the set of transceivers.