Computer interface apparatus using split-cycle lookahead addressing for faster access to paged memory

Claim 1

In an apparatus for decreasing the access time to addressable memories containing pages of stored data addressable through real addresses, when virtual addressing is used wherein the apparatus uses a memory bus, at least one bank of addressable memory for storing pages of addressable data, a processor means coupled to the memory bus for providing a virtual address consisting of high and low order bits wherein the lower order bits correspond to real address bits and the higher order bits are translatable to real address bits, an address translator means coupled to the memory bus for translating the provided virtual addresses into real addresses and for forwarding the real address to the memory bus, and a memory interface means for interfacing the addressable memory to the memory bus, the improvement in the memory interface means comprising; first means for receiving and gating said lower order virtual address bits to said addressable memory to commence memory access prior to the completion of translation by said address translator; second means for receiving and gating the translated higher order bits of said provided virtual address corresponding to the real address from said memory bus to said addressable memory to complete memory addressing; a decoder operatively coupled to said second means for receiving and converting select higher order address bits into addressable memory bank select signals; a first logic means responsive to a virtual address on said memory bus for controlling said first and said second means to cause said first and said second means to hold the high and the low order virtual address bits present on said memory bus during a first cycle and to hold the translated virtual address bits present on said memory bus during a second cycle; and multiplexer means coupled to said first and said second means for receiving and alternately gating to said addressable memory the held low order virtual address bits during said first cycle and the held high order translated address bits during said second cycle.