Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures

Claim 1

A method of planarizing a microelectronic circuit, comprising the steps of: (a) forming a planarizing layer over said microelectronic circuit, the planarizing layer initially having an irregular top surface; (b) depositing a glass layer over said top surface of the planarizing layer such that the glass layer initially has an irregular top surface; (c) polishing the glass layer and any portions of the planarizing layer that become exposed through the glass layer until they become substantially planar; (d) maintaining the glass layer below a reflow temperature thereof while performing steps (b) and (c); and between steps (b) and (c), the step of: (e) densifying the glass layer at a temperature below said reflow temperature.

Claim 2

A method of planarizing a microelectronic circuit, comprising the steps of: (a) forming a planarizing layer over said microelectronic circuit, the planarizing layer initially having an irregular top surface; (b) depositing a glass layer over said top surface of the planarizing layer such that the glass layer initially has an irregular top surface; (c) polishing the glass layer and any portions of the planarizing layer that become exposed through the glass layer until they become substantially planar; (d) maintaining the glass layer below a reflow temperature thereof while performing steps (b) and (c); and between steps (b) and (c), the step of: (e) densifying the glass layer at a temperature below said reflow temperature.

Claim 11

A method of planarizing a microelectronic circuit, comprising the steps of: (a) forming a planarizing layer over said microelectronic circuit, the planarizing layer initially having an irregular top surface; (b) depositing a glass layer over said top surface of the planarizing layer such that the glass layer initially has an irregular top surface; (c) polishing the glass layer and any portions of the planarizing layer that become exposed through the glass layer until they become substantially planar; and (d) maintaining the glass layer below a reflow temperature thereof while performing steps (b) and (c), in which: step (b) comprises depositing the glass layer as including BPSG; and step (d) comprises maintaining the glass layer at or below a temperature of approximately 800° C.; and step (b) comprises depositing the glass layer at a temperature of approximately 700°-800° C.

Claim 12

A method of planarizing a microelectronic circuit, comprising the steps of: (a) forming a planarizing layer over said microelectronic circuit, the planarizing layer initially having an irregular top surface; (b) depositing a glass layer over said top surface of the planarizing layer such that the glass layer initially has an irregular top surface; (c) polishing the glass layer and any portions of the planarizing layer that become exposed through the glass layer until they become substantially planar; and (d) maintaining the glass layer below a reflow temperature thereof while performing steps (b) and (c), in which: step (b) comprises depositing the glass layer as including BPSG; and step (d) comprises maintaining the glass layer at or below a temperature of approximately 800° C.; and step (b) comprises depositing the glass layer at a temperature of approximately 700°-800° C.

Claim 13

A method of fabricating a CMOS microelectronic circuit on a surface of a semiconductor substrate having first and second well regions, comprising: forming a silicon nitride layer over the surface; patterning the silicon nitride layer to have an opening over the first well region and a nitride segment over the second well region; implanting a first dopant of a first conductivity type into the substrate through the opening into the first well region, the nitride segment substantially shielding implantation of the first dopant into the second well region; growing a first silicon dioxide layer over the surface in the opening over the first well region, the nitride segment substantially inhibiting growth of silicon dioxide in the second well region; removing the silicon nitride layer; implanting a second dopant of a second conductivity type into the substrate, the first silicon dioxide layer substantially shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate oxide layers over channel regions in the first and second well regions respectively; forming gates over the gate oxide layers respectively; forming source and drain regions in each of the first and second well regions on opposite sides of the channel regions respectively; forming a second silicon dioxide layer over the surface and the gates which is relatively thick between the first and second well regions and is relatively thin in remaining areas over the surface, a surface of the second layer of silicon dioxide having irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a surface of the third silicon dioxide layer having irregular topology; depositing a glass layer over said top surface of the third silicon dioxide layer such that the glass layer initially has an irregular top surface; polishing the glass layer and any portions of the third silicon dioxide layer that become exposed through the glass layer until they become substantially planar; and maintaining the glass layer below a reflow temperature thereof while performing said deposition and said polishing; and the step, performed between said depositing and said polishing, of densifying the glass layer at a temperature below said reflow temperature.

Claim 14

A method of fabricating a CMOS microelectronic circuit on a surface of a semiconductor substrate having first and second well regions, comprising: forming a silicon nitride layer over the surface; patterning the silicon nitride layer to have an opening over the first well region and a nitride segment over the second well region; implanting a first dopant of a first conductivity type into the substrate through the opening into the first well region, the nitride segment substantially shielding implantation of the first dopant into the second well region; growing a first silicon dioxide layer over the surface in the opening over the first well region, the nitride segment substantially inhibiting growth of silicon dioxide in the second well region; removing the silicon nitride layer; implanting a second dopant of a second conductivity type into the substrate, the first silicon dioxide layer substantially shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate oxide layers over channel regions in the first and second well regions respectively; forming gates over the gate oxide layers respectively; forming source and drain regions in each of the first and second well regions on opposite sides of the channel regions respectively; forming a second silicon dioxide layer over the surface and the gates which is relatively thick between the first and second well regions and is relatively thin in remaining areas over the surface, a surface of the second layer of silicon dioxide having irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a surface of the third silicon dioxide layer having irregular topology; depositing a glass layer over said top surface of the third silicon dioxide layer such that the glass layer initially has an irregular top surface; polishing the glass layer and any portions of the third silicon dioxide layer that become exposed through the glass layer until they become substantially planar; and maintaining the glass layer below a reflow temperature thereof while performing said deposition and said polishing; and the step, performed between said depositing and said polishing, of densifying the glass layer at a temperature below said reflow temperature.

Claim 16

A method of fabricating a CMOS microelectronic circuit on a surface of a semiconductor substrate having first and second well regions, comprising: forming a silicon nitride layer over the surface; patterning the silicon nitride layer to have an opening over the first well region and a nitride segment over the second well region; implanting a first dopant of a first conductivity type into the substrate through the opening into the first well region, the nitride segment substantially shielding implantation of the first dopant into the second well region; growing a first silicon dioxide layer over the surface in the opening over the first well region, the nitride segment substantially inhibiting growth of silicon dioxide in the second well region; removing the silicon nitride layer; implanting a second dopant of a second conductivity type into the substrate, the first silicon dioxide layer substantially shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate oxide layers over channel regions in the first and second well regions respectively; forming gates over the gate oxide layers respectively; forming source and drain regions in each of the first and second well regions on opposite sides of the channel regions respectively; forming a second silicon dioxide layer over the surface and the gates which is relatively thick between the first and second well regions and is relatively thin in .remaining areas over the surface, a surface of the second layer of silicon dioxide having irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a surface of the third silicon dioxide layer having irregular topology; depositing a glass layer over said top surface of the third silicon dioxide layer such that the glass layer initially has an irregular top surface; polishing the glass layer and any portions of the third silicon dioxide layer that become exposed through the glass layer until they become substantially planar; maintaining the glass layer below a reflow temperature thereof while performing said deposition and said polishing; forming a fourth silicon dioxide layer over the third silicon dioxide layer; forming first vias through the fourth, third and second silicon dioxide layers; forming metal plugs in the first vias to contact the source and drain regions respectively; forming a fifth silicon dioxide layer over the fourth silicon dioxide layer and over the metal plugs, a surface of the fifth silicon dioxide layer having troughs and irregularities; forming a filler glass layer over the fifth silicon dioxide layer to smooth the troughs and irregularities; forming a sixth silicon dioxide layer over the filler glass layer silicon dioxide layer and portions of the fifth silicon dioxide layer that are exposed through the filler glass layer; forming second vias through the sixth and fifth silicon dioxide layers; applying a barrier metal layer that fills the second vias over the sixth silicon dioxide layer; applying a metal filler over the barrier metal layer; applying a metal cap over the metal filler; and applying a passivation layer over the metal cap and the sixth silicon dioxide layer.

Claim 17

A method of fabricating a CMOS microelectronic circuit on a surface of a semiconductor substrate having first and second well regions, comprising: forming a silicon nitride layer over the surface; patterning the silicon nitride layer to have an opening over the first well region and a nitride segment over the second well region; implanting a first dopant of a first conductivity type into the substrate through the opening into the first well region, the nitride segment substantially shielding implantation of the first dopant into the second well region; growing a first silicon dioxide layer over the surface in the opening over the first well region, the nitride segment substantially inhibiting growth of silicon dioxide in the second well region; removing the silicon nitride layer; implanting a second dopant of a second conductivity type into the substrate, the first silicon dioxide layer substantially shielding implantation of the second dopant into the first well region; removing the first silicon dioxide layer; forming gate oxide layers over channel regions in the first and second well regions respectively; forming gates over the gate oxide layers respectively; forming source and drain regions in each of the first and second well regions on opposite sides of the channel regions respectively; forming a second silicon dioxide layer over the surface and the gates which is relatively thick between the first and second well regions and is relatively thin in .remaining areas over the surface, a surface of the second layer of silicon dioxide having irregular topology; forming a third silicon dioxide layer over the second silicon dioxide layer, a surface of the third silicon dioxide layer having irregular topology; depositing a glass layer over said top surface of the third silicon dioxide layer such that the glass layer initially has an irregular top surface; polishing the glass layer and any portions of the third silicon dioxide layer that become exposed through the glass layer until they become substantially planar; maintaining the glass layer below a reflow temperature thereof while performing said deposition and said polishing; forming a fourth silicon dioxide layer over the third silicon dioxide layer; forming first vias through the fourth, third and second silicon dioxide layers; forming metal plugs in the first vias to contact the source and drain regions respectively; forming a fifth silicon dioxide layer over the fourth silicon dioxide layer and over the metal plugs, a surface of the fifth silicon dioxide layer having troughs and irregularities; forming a filler glass layer over the fifth silicon dioxide layer to smooth the troughs and irregularities; forming a sixth silicon dioxide layer over the filler glass layer silicon dioxide layer and portions of the fifth silicon dioxide layer that are exposed through the filler glass layer; forming second vias through the sixth and fifth silicon dioxide layers; applying a barrier metal layer that fills the second vias over the sixth silicon dioxide layer; applying a metal filler over the barrier metal layer; applying a metal cap over the metal filler; and applying a passivation layer over the metal cap and the sixth silicon dioxide layer.