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US4450021A Expired / Lapsed US ⏱️ 0.0 years remaining

Mask diffusion process for forming Zener diode or complementary field effect transistors

Assignee: AMI Semiconductor Inc
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Filing: 1982-02-22
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Granted: 1984-05-22
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Expires: 2002-02-22
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Abstract

Abstract A unique fabrication method allows the formation of regions of opposite conductivity types in a semiconductor substrate 100 utilizing a single masking step. A first mask is formed on the surface of the semiconductor substrate and patterned to define the regions (110) which are to be doped to a first conductivity type. Subsequent to the doping of these first regions, a protective layer (111) is formed over these first regions. The mask is then removed, thus exposing the regions (112) which are to be doped to the second conductivity type opposite to said first conductivity type. These exposed regions are then doped to said opposite conductivity type, with the first regions which have been doped to said first conductivity type protected by said protective layer.

Inventors

  • 👤 Tarsaim L. Batra
  • 👤 Scott Bowden

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:46
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S438/00; Y10S438/983

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 207 words
The method of forming a complementary metal oxide-silicon device within a substrate of first conductivity type comprising the steps of: forming within said substrate a well region of a second conductivity type which is opposite said first conductivity type; forming a field region in all areas where active devices are not to be formed, thus exposing active regions on the surface of said substrate in which active devices are to be formed; forming a gate dielectric layer within said active regions; forming a gate region on said gate dielectric layer; masking said substrate with a first protective layer; patterning said first protective layer and said gate insulation layer to expose only those active regions on the surface of said well region; doping source and drain regions to said first conductivity type within said well region which are not protected by said gate regions or said field regions; forming a second protective layer on the surface of said substrate not protected by said first protective layer, said field region or said gate region; removing said first protective layer; and doping source and drain regions to a second conductivity type within said substrate which are not protected by said second protective layer, said field region or said gate region.
Claim 2
Independent Claim 207 words
The method of forming a complementary metal oxide-silicon device within a substrate of first conductivity type comprising the steps of: forming within said substrate a well region of a second conductivity type which is opposite said first conductivity type; forming a field region in all areas where active devices are not to be formed, thus exposing active regions on the surface of said substrate in which active devices are to be formed; forming a gate dielectric layer within said active regions; forming a gate region on said gate dielectric layer; masking said substrate with a first protective layer; patterning said first protective layer and said gate insulation layer to expose only those active regions on the surface of said well region; doping source and drain regions to said first conductivity type within said well region which are not protected by said gate regions or said field regions; forming a second protective layer on the surface of said substrate not protected by said first protective layer, said field region or said gate region; removing said first protective layer; and doping source and drain regions to a second conductivity type within said substrate which are not protected by said second protective layer, said field region or said gate region.
Claim 3
Independent Claim 137 words
The method of forming a PN junction within a substrate and near the surface of said substrate comprising the steps of: forming a mask on the surface of said substrate to expose a first region of said substrate where it is desired to introduce a dopant of a first conductivity type; introducing dopant of said first conductivity type into said substrate, wherein said dopant of said first conductivity type is formed within said first region; forming a protective layer on the surface of said first region; removing said mask from said substrate; and introducing dopant of a second conductivity type into said substrate, wherein said dopant of said second conductivity type is formed within a second region of said substrate which had not been exposed by said mask, said second region lying adjacent to said first region.
Claim 4
Independent Claim 137 words
The method of forming a PN junction within a substrate and near the surface of said substrate comprising the steps of: forming a mask on the surface of said substrate to expose a first region of said substrate where it is desired to introduce a dopant of a first conductivity type; introducing dopant of said first conductivity type into said substrate, wherein said dopant of said first conductivity type is formed within said first region; forming a protective layer on the surface of said first region; removing said mask from said substrate; and introducing dopant of a second conductivity type into said substrate, wherein said dopant of said second conductivity type is formed within a second region of said substrate which had not been exposed by said mask, said second region lying adjacent to said first region.
Claim 5
Dependent Claim 19 words
The method of claim 2 wherein said first conductivity type is N and said second conductivity type is P.
Claim 6
Dependent Claim 19 words
The method of claim 2 wherein said first conductivity type is P and said second conductivity type is N.
Claim 7
Dependent Claim 13 words
The method of claim 2 wherein said PN junction comprises a zener diode.

References Cited (Backward Citations)

US3677838A Cited
US3928081A Cited
US4099998A Cited
US4277291A Cited
US4306916A Cited
US4295897A Cited
US4295897B1 Cited
US4381956A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-05-22 1987-11-21 1988-05-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-05-22 1991-11-21 1992-05-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-05-22 1995-11-21 1996-05-22 $7700.00 Window Closed / Lapsed

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