EP0356202A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Mosfet and fabrication method
Assignee: Inmos Ltd
•
Filing: 1989-08-22
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Granted: —
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Expires: 2009-08-22
Abstract
Abstract A method of fabricating a MOSFET wherein sidewall spacers are provided adjacent the gate of the MOSFET, the method including the steps of providing an insulating layer which extends over the source, drain and gate of the MOSFET and which acts as an impurity diffusion barrier; and forming on the insulating layer sidewall spacers which are composed of an insulating material.
Inventors
- 👤 Richard Norman Campbell
- 👤 Michael Kevin Thompson
- 👤 Robert Paul Haase
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 01:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
61 words
A method of fabricating a MOSFET wherein sidewall spacers are provided adjacent the gate of the MOSFET, the method including the steps of providing an insulating layer which extends over the source, drain and gate of the MOSFET and which acts as an impurity diffusion barrier; and forming on the insulating layer sidewall spacers which are composed of an insulating material.
Claim 2
Independent Claim
61 words
A method of fabricating a MOSFET wherein sidewall spacers are provided adjacent the gate of the MOSFET, the method including the steps of providing an insulating layer which extends over the source, drain and gate of the MOSFET and which acts as an impurity diffusion barrier; and forming on the insulating layer sidewall spacers which are composed of an insulating material.
Claim 3
Dependent Claim
15 words
A method according to claim 1, wherein the insulating layer is composed of silicon nitride.
Claim 4
Dependent Claim
18 words
A method according to Claim 1 or Claim 2 wherein the sidewall spacers are composed of silicon oxide.
Claim 5
Independent Claim
131 words
A method of fabricating a MOSFET, which method includes the steps of:- (a) providing a gate for a MOSFET on an oxide layer which extends over a region of silicon doped with an impurity of one conductivity type; (b) forming on the gate and adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming a second oxide layer over the insulating layer; (d) anisotropically etching the second oxide layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gate; and (e) implanting a dopant impurity of a second conductivity type into the region of silicon, the sidewall spacers acting to mask portions of the region which are located under the sidewall spacers.
Claim 6
Independent Claim
131 words
A method of fabricating a MOSFET, which method includes the steps of:- (a) providing a gate for a MOSFET on an oxide layer which extends over a region of silicon doped with an impurity of one conductivity type; (b) forming on the gate and adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming a second oxide layer over the insulating layer; (d) anisotropically etching the second oxide layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gate; and (e) implanting a dopant impurity of a second conductivity type into the region of silicon, the sidewall spacers acting to mask portions of the region which are located under the sidewall spacers.
Claim 7
Dependent Claim
41 words
A method according to claim 4, further including the steps of:- (f) isotropically etching the sidewall spacers from the insulating layer; and (g) implanting a dopant impurity of the second conductivity type into the said portions of the region of silicon.
Claim 8
Dependent Claim
22 words
A method according to claim 5, wherein the implanting steps (e) and (g) are adapted to produce a lightly doped drain MOSFET.
Claim 9
Independent Claim
20 words
A method according to any one of claims 4 to 6, wherein the insulating layer is composed of silicon nitride.
Claim 10
Independent Claim
21 words
A method according to any one of claims 4 to 7, wherein the second oxide layer is composed of silicon oxide.
Claim 11
Independent Claim
280 words
A method of fabricating complementary p-channel and n-channel MOSFETS, the method comprising the steps of:- (a) providing gates for complementary p-channel and n-channel MOSFETS, each gate being located on a respective oxide layer which extends over a respective region of silicon doped with respectively, an n- or p-type impurity, the gates being separated by a region of isolation oxide; (b) forming on the gates and the adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming over the insulating layer an etchable layer composed of an insulating material; and (d) anisotropically etching the etchable layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gates; wherein the n-channel MOSFET is a lightly doped drain MOSFET and is fabricated by steps (e) to (i):- (e) masking the n-regions of silicon; (f) implanting an n+ type dopant impurity into the unmasked p-region of silicon, the sidewall spacers in the p-region acting to mask portions of the p-region which are located under the said sidewall spacers; (g) isotropically etching the said sidewall spacers from the insulating layer; (h) implanting an n⁻ type dopant impurity into the said portions of the p-region; and (i) unmasking the n-region of silicon; and wherein the p-channel MOSFET is fabricated either before or after the n-channel MOSFET by steps (j) to (l):- (j) masking the p-region of silicon; (k) implanting a p+ type dopant impurity into the unmasked n-region of silicon, the sidewall spacers in the n-region acting to mask portions of the n-region which are located under the said sidewall spacers; and (l) unmasking the p-region of silicon.
Claim 12
Independent Claim
280 words
A method of fabricating complementary p-channel and n-channel MOSFETS, the method comprising the steps of:- (a) providing gates for complementary p-channel and n-channel MOSFETS, each gate being located on a respective oxide layer which extends over a respective region of silicon doped with respectively, an n- or p-type impurity, the gates being separated by a region of isolation oxide; (b) forming on the gates and the adjacent exposed portions of the oxide layer an insulating layer which acts as a barrier to diffusion of impurities in silicon; (c) forming over the insulating layer an etchable layer composed of an insulating material; and (d) anisotropically etching the etchable layer to provide sidewall spacers of the etchable layer on the insulating layer and adjacent the gates; wherein the n-channel MOSFET is a lightly doped drain MOSFET and is fabricated by steps (e) to (i):- (e) masking the n-regions of silicon; (f) implanting an n+ type dopant impurity into the unmasked p-region of silicon, the sidewall spacers in the p-region acting to mask portions of the p-region which are located under the said sidewall spacers; (g) isotropically etching the said sidewall spacers from the insulating layer; (h) implanting an n⁻ type dopant impurity into the said portions of the p-region; and (i) unmasking the n-region of silicon; and wherein the p-channel MOSFET is fabricated either before or after the n-channel MOSFET by steps (j) to (l):- (j) masking the p-region of silicon; (k) implanting a p+ type dopant impurity into the unmasked n-region of silicon, the sidewall spacers in the n-region acting to mask portions of the n-region which are located under the said sidewall spacers; and (l) unmasking the p-region of silicon.
Claim 13
Dependent Claim
16 words
A method according to claim 9 further comprising the steps, between steps (k) and (l), of:-
Claim 14
Dependent Claim
11 words
(k′) isotropically etching the sidewall spacers from the insulating layer; and
Claim 15
Dependent Claim
11 words
(k′) isotropically etching the sidewall spacers from the insulating layer; and
Claim 16
Dependent Claim
24 words
(k˝) implanting a p⁻ dopant impurity into the said portions of the n-region of silicon, thereby to produce a lightly doped drain p-channel MOSFET.
Claim 17
Dependent Claim
24 words
(k˝) implanting a p⁻ dopant impurity into the said portions of the n-region of silicon, thereby to produce a lightly doped drain p-channel MOSFET.
Claim 18
Dependent Claim
32 words
A method according to claim 9 further comprising the step, after step (l) of:- (l′) diffusing the p+ implant towards the respective gate thereby to produce a zero drain overlap p-channel MOSFET.
Claim 19
Dependent Claim
46 words
A method according to claim 9 further comprising the step, before step (b), of depositing on the region of isolation oxide a structure to form a resistive element, and wherein in step (b) the insulating layer is formed over the isolation oxide and the said structure.
Claim 20
Independent Claim
20 words
A method according to any one of claims 9 to 12, wherein the insulating layer is composed of silicon nitride.
Claim 21
Independent Claim
20 words
A method according to any one of claims 9 to 13, wherein the etchable layer is composed of silicon oxide.
Claim 22
Dependent Claim
43 words
A semiconductor device including complementary MOSFETS comprising a lightly doped drain n-channel MOSFET and a zero drain overlap p-channel MOSFET, each MOSFET having an insulating layer extending over the source, drain and gate thereof, the insulating layer acting as an impurity diffusion barrier.
Claim 23
Dependent Claim
43 words
A semiconductor device including complementary MOSFETS comprising a lightly doped drain n-channel MOSFET and a zero drain overlap p-channel MOSFET, each MOSFET having an insulating layer extending over the source, drain and gate thereof, the insulating layer acting as an impurity diffusion barrier.
Claim 24
Dependent Claim
28 words
A semiconductor device according to claim 15 further comprising sidewall spacers which are disposed on the insulating layer adjacent the gate of the zero drain overlap p-channel MOSFET.
Claim 25
Dependent Claim
32 words
A semiconductor device according to claim 15 or claim 16 further comprising a resistive element which is disposed beneath the insulating layer above a region of isolation oxide of the semiconductor device.
References Cited (Backward Citations)
No citation records indexed.
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