US5073509A
Expired / Lapsed
US
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Blanket CMOS channel-stop implant
Assignee: Micron Technology Inc
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Filing: 1989-12-11
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Granted: 1991-12-17
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Expires: 2009-12-11
Abstract
Abstract A CMOS transistor is fabricated by forming the n-wells with both phosphorus and arsenic implants. The arsenic, with its lower diffusion coefficient, tends to concentrate near the top surface of the n-wells, with the phosphorus penetrating sufficiently to define the n-wells at the desired depth. A boron channel stop implant is later applied without masking over the n-wells. Since the arsenic implant is concentrated near the surface, the arsenic impurities overcome the effects of the boron impurities.
Inventors
- 👤 Ruojia R. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:11
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
161 words
Method of fabricating transistor circuits having complimentary p-channel and n-channel transistors, in which n-wells are formed in a semiconductor wafer in areas at which p-type transistors are formed, the n-wells being defined by implanting the wafer with conductive impurities sufficiently to define the n-wells, and areas of the wafer outside of the n-wells being p areas, characterized by: a) applying a supplemental dopant implant material to the n-wells as n-type conductive impurity, the supplemental implant material having a diffusion coefficient which is less than that of the implant material used to define the n-wells; b) applying a p-type impurity to the wafer in a maskless implant step which is sufficient to result in p+ areas being formed outside of the n-wells, but insufficient to overcome the dopant effects within the n wells of the supplemental implant, thereby resulting in the n-wells remaining as n-type material, as a result of the supplemental implant; c) growing field oxide areas on the p areas.
Claim 2
Dependent Claim
161 words
Method of fabricating transistor circuits having complimentary p-channel and n-channel transistors, in which n-wells are formed in a semiconductor wafer in areas at which p-type transistors are formed, the n-wells being defined by implanting the wafer with conductive impurities sufficiently to define the n-wells, and areas of the wafer outside of the n-wells being p areas, characterized by: a) applying a supplemental dopant implant material to the n-wells as n-type conductive impurity, the supplemental implant material having a diffusion coefficient which is less than that of the implant material used to define the n-wells; b) applying a p-type impurity to the wafer in a maskless implant step which is sufficient to result in p+ areas being formed outside of the n-wells, but insufficient to overcome the dopant effects within the n wells of the supplemental implant, thereby resulting in the n-wells remaining as n-type material, as a result of the supplemental implant; c) growing field oxide areas on the p areas.
Claim 3
Dependent Claim
67 words
Method of fabricating transistor circuits as described in claim 1, further characterized by: the choice of implant materials being made in accordance with the diffusion coefficient of the dopant to cause the distribution of the dopant to result in a relatively high concentration of minority carriers closer to a top surface and a lesser concentration of minority carriers to a desired depth further form the top surface.
Claim 4
Dependent Claim
48 words
Method of fabricating transistor circuits as described in claim 2, further characterized by: the material used to define the n-wells having a relatively high diffusion coefficient, as compared to the supplemental implant material, to the extent that the supplemental implant concentrates at a particular level within the n-wells.
Claim 5
Dependent Claim
48 words
Method of fabricating transistor circuits as described in claim 1, further characterized by: the material used to define the n-wells having a relatively high diffusion coefficient, as compared to the supplemental implant material, to the extent that the supplemental implant concentrates at a particular level within the n-wells.
Claim 6
Dependent Claim
30 words
Method of fabricating transistor circuits as described in claim 1, further characterized by: the implant material used to define the n-wells being phosphorus and the supplemental implant material being arsenic.
Claim 7
Dependent Claim
165 words
Method of fabricating a semiconductor random access memory array having complimentary p-channel and n-channel transistors, in which n-wells are formed in a semiconductor wafer in areas at which p=type transistors are formed, the n-wells being defined by implanting the wafer with impurities sufficiently to define the n-wells, and areas of the wafer outside of the n-wells being p areas, characterized by: a) applying a supplemental dopant implant material to the n-wells as an n-type conductive impurity, the supplemental implant material having a diffusion coefficient which is less than that of the implant material used to define the n-wells; b) applying a p-type impurity to the wafer in a maskless implant step which is sufficient to result in p+ areas being formed outside of the n-wells, but insufficient to overcome the dopant effects within the n wells of the supplemental implant, thereby resulting in the n-wells remaining as n-type material, as a result of the supplemental implant; c) growing field oxide areas on the p areas.
Claim 8
Dependent Claim
165 words
Method of fabricating a semiconductor random access memory array having complimentary p-channel and n-channel transistors, in which n-wells are formed in a semiconductor wafer in areas at which p=type transistors are formed, the n-wells being defined by implanting the wafer with impurities sufficiently to define the n-wells, and areas of the wafer outside of the n-wells being p areas, characterized by: a) applying a supplemental dopant implant material to the n-wells as an n-type conductive impurity, the supplemental implant material having a diffusion coefficient which is less than that of the implant material used to define the n-wells; b) applying a p-type impurity to the wafer in a maskless implant step which is sufficient to result in p+ areas being formed outside of the n-wells, but insufficient to overcome the dopant effects within the n wells of the supplemental implant, thereby resulting in the n-wells remaining as n-type material, as a result of the supplemental implant; c) growing field oxide areas on the p areas.
Claim 9
Dependent Claim
68 words
Method of fabricating semiconductor memory array as described in claim 6, further characterized by: the choice of implant materials being made in accordance with the diffusion coefficient of the dopant to cause the distribution of the dopant to result in a relatively high concentration of minority carriers closer to a top surface and a lesser concentration of minority carriers to a desired depth further form the top surface.
Claim 10
Dependent Claim
49 words
Method of fabricating semiconductor memory array as described in claim 7, further characterized by: the material used to define the n-wells having a relatively high diffusion coefficient, as compared to the supplemental implant material, to the extent that the supplemental implant concentrates at a particular level within the n-wells.
Claim 11
Dependent Claim
49 words
Method of fabricating semiconductor memory array as described in claim 6, further characterized by: the material used to define the n-wells having a relatively high diffusion coefficient, as compared to the supplemental implant material, to the extent that the supplemental implant concentrates at a particular level within the n-wells.
Claim 12
Dependent Claim
32 words
Method of fabricating a semiconductor memory array as described in claim 6, further characterized by: the implant material used to define the n-wells being phosphorus and the supplemental implant material being arsenic.
References Cited (Backward Citations)
US4554726A
Cited
US4839301A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |