Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants

Claim 1

Method of fabricating transistor circuits having complimentary p-channel and n-channel transistors, in which n-wells are formed in a semiconductor wafer in areas at which p-type transistors are formed, the n-wells being defined by implanting the wafer with impurities sufficiently to define the n-wells, and areas of the wafer outside of the n-wells being p areas, the method characterized by: (a) applying a supplemental implant material to the areas at which p type transistors are formed, the supplemental implant material being an n type dopant and having a diffusion coefficient which is less than that of the implant material used to define the n-wells; (b) applying an impurity to the wafer which is sufficient to result in p areas being formed outside of the n-wells, but insufficient to overcome the definition of the n-wells where the supplemental implant is applied, said insufficiency resulting in p areas not being formed in the n-wells because said impurity is counteracted by the supplemental implant; (c) growing field oxide areas on the p areas; (d) masking the n-wells; (e) applying a high energy implant of dopant to the p areas subsequent to said growth of field oxide areas and said masking; and (f) said high energy implant being sufficient to pass through the field oxide areas on the p areas.