Patent US5501994A successfully refreshed from Google Patents.
US5501994A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Extended drain resurf lateral DMOS devices
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1996-03-26
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Expires: 2015-06-07
Abstract
Abstract An integrated circuit containing high voltage PMOS and/or NMOS devices as well as low voltage PMOS and/or NMOS devices and a simple low cost method for making same that is adaptable to many types of semiconductor processes; furthermore, the breakdown voltage of the high voltage devices is easily adjusted so that the value of Ron can be optimized. High voltage MOS devices 6 and 7 are formed on substrate 10 using essentially the same process steps as are used to form low voltage MOS devices 8 and 9. Low values of Ron are obtained by selecting impurity concentration levels for HV drift region n-tank 21 and for HV drift region p-tank 41 so that the depletion region distance D1 bounded by equipotential lines 301a and 301j and the depletion region distance D1a bounded by equipotential lines 401a and 401h are smaller than the physical size D2 and D2a of drift regions 41 and 21, respectively.
Inventors
- 👤 Chia-Cu P. Mei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:22
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/835; H10D84/85; H10D84/856
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
135 words
A method for making a high voltage transistor comprising: forming a well in a semiconductive substrate, said well having a first impurity concentration level; forming a drift region in said well, said drift region having a second impurity concentration level which is opposite to said first impurity concentration level, said second impurity concentration level having a value which will result in the formation of a depletion region when an operating voltage is applied which is not substantially larger than needed to withstand a breakdown voltage that said high voltage transistor is designed to withstand; forming a drain in said drift region such that an extended drain will be formed in said drift region between said drain and said depletion region when said operating voltage is applied to said drain whereby R ds (on) is minimized.
Claim 2
Independent Claim
135 words
A method for making a high voltage transistor comprising: forming a well in a semiconductive substrate, said well having a first impurity concentration level; forming a drift region in said well, said drift region having a second impurity concentration level which is opposite to said first impurity concentration level, said second impurity concentration level having a value which will result in the formation of a depletion region when an operating voltage is applied which is not substantially larger than needed to withstand a breakdown voltage that said high voltage transistor is designed to withstand; forming a drain in said drift region such that an extended drain will be formed in said drift region between said drain and said depletion region when said operating voltage is applied to said drain whereby R ds (on) is minimized.
Claim 3
Dependent Claim
36 words
The method of claim 1, in which: said first impurity concentration level is in the range of about 1e15-5e 16/cm 3 p-type; and said second impurity concentration is in the range of about 5e16-5e17/cm 3 n-type.
Claim 4
Dependent Claim
27 words
The method of claim 1, in which: said first impurity concentration level is about 2e16/cm 3 p-type; and said second impurity concentration is about 3e17/cm a n-type.
Claim 5
Dependent Claim
35 words
The method of claim 1, in which: said first impurity concentration level is in the range of about 1e15-5e16/cm 3 n-type; and said second impurity concentration is in the range of about 1e16-3e17/cm 3 p-type.
Claim 6
Dependent Claim
27 words
The method of claim 1, in which: said first impurity concentration level is about 1.5e16/cm 3 n-type; and said second impurity concentration is about 8e16/cm e p-type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |