Semiconductor memory

Claim 2

A semiconductor memory device comprising: a memory cell array formed of a plurality of dynamic memory cell units on a semiconductor substrate, each of said dynamic memory cell units including: a first data node; a first cascade gate connected to said first data node and including a plurality of first MOS transistors which are connected in cascade; a plurality of data storage capacitors each having a first electrode respectively connected to a corresponding one of said first MOS transistors at an end of said corresponding one of said first MOS transistors which is remote from said first data node; word lines each respectively connected to a gate of a corresponding one of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors; and isolation MOS transistors respectively transistor formed between dynamic memory cell units which are arranged side by side on said semiconductor substrate.

Claim 3

A semiconductor memory device comprising: a first data node; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, connected to said first data node and including a plurality of first MOS transistors which are connected in cascade, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a corresponding one of said first MOS transistors at an end of said corresponding one of said first MOS transistors which is remote from said first data node; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of the corresponding one of said first MOS transistors.

Claim 4

A semiconductor memory device comprising: a first data node; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, connected to said first data node and including a plurality of first MOS transistors which are connected in cascade, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a corresponding one of said first MOS transistors at an end of said corresponding one of said first MOS transistors which is remote from said first data node; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of the corresponding one of said first MOS transistors.

Claim 5

A semiconductor memory device comprising: a memory cell array formed of a plurality of dynamic memory cell units, each of said dynamic memory cell units including: a first data node; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, connected to said first data node and including a plurality of first MOS transistors which are connected in cascade, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a corresponding one of said first MOS transistors at an end of said corresponding one of said first MOS transistors which is remote from said first data node; isolation MOS transistors respectively transistor formed between dynamic memory cell units which are arranged side by side on said semiconductor substrate; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of the corresponding one of said first MOS transistors.

Claim 6

A semiconductor memory device comprising: a memory cell array formed of a plurality of dynamic memory cell units, each of said dynamic memory cell units including: a first data node; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, connected to said first data node and including a plurality of first MOS transistors which are connected in cascade, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a corresponding one of said first MOS transistors at an end of said corresponding one of said first MOS transistors which is remote from said first data node; isolation MOS transistors respectively transistor formed between dynamic memory cell units which are arranged side by side on said semiconductor substrate; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of the corresponding one of said first MOS transistors.

Claim 7

The semiconductor memory device according to claim 1, in which each of said cascade-connected first MOS transistors has an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate, the active regions of said cascade-connected first MOS transistors being arranged linearly on said semiconductor substrate, said first electrode of each of said data storage capacitors comprising a charge storage electrode, each of said data storage capacitors further including an insulating film, and a plate electrode and having a stack structure wherein said charge storage electrode is in contact with the source region or the drain region of the corresponding one of said first MOS transistors.

Claim 8

The semiconductor memory device according to claim 2, in which the active regions of said cascade-connected first MOS transistors are arranged linearly on said semiconductor substrate, and each of said data storage capacitors further includes an insulating film and a plate electrode and has a stack structure wherein said charge storage electrode is in contact with the source region or the drain region of the corresponding one of said first MOS transistors.

Claim 9

The semiconductor memory device according to claim 3, in which the active regions of said cascade-connected first MOS transistors are arranged linearly on said semiconductor substrate, and each of said data storage capacitors further includes an insulating film and a plate electrode and has a stack structure wherein said storage electrode is in contact with the source region or the drain region of the corresponding one of said first MOS transistors.

Claim 10

A semiconductor memory device, comprising: first and second data nodes; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, including at least three first MOS transistors connected in cascade between said first and second data nodes, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a node between adjacent ones of said first MOS transistors; word lines each respectively connected to a gate of a corresponding one of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of a corresponding one of said first MOS transistors.

Claim 11

A semiconductor memory device, comprising: first and second data nodes; a first cascade gate, having a cascade gate active region defined on a semiconductor substrate, including at least three first MOS transistors connected in cascade between said first and second data nodes, each of said first MOS transistors having an active region defined by a source region, a drain region, and a channel region on said semiconductor substrate; a plurality of data storage capacitors each having a first electrode respectively connected to a node between adjacent ones of said first MOS transistors; word lines each respectively connected to a gate of a corresponding one of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors; and a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node, wherein the first electrode of each of said data storage capacitors comprises a charge storage electrode which is in contact with an end of the active region of a corresponding one of said first MOS transistors.

Claim 12

The semiconductor memory device according to claim 7, in which the active regions of said cascade-connected first MOS transistors are arranged linearly on said semiconductor substrate, and each of said data storage capacitors further includes an insulating film and a plate electrode and has a stack structure wherein said charge storage electrode is in contact with the source region or the drain region of a corresponding one of said first MOS transistors.

Claim 13

The semiconductor memory device according to any one of claims 1, 3, 4, and 6, in which gate electrodes of said isolation MOS transistors are formed on a same wiring layer as gate electrodes of said cascade-connected first MOS transistors.

Claim 14

The semiconductor memory device according to any one of claims 2, 3, 5, 6, 7, and 8 in which said conductor which is in contact with an end of said cascade gate active region is formed on a same wiring layer as said charge storage electrodes of said data storage capacitors.

Claim 15

The semiconductor memory device according to any one of claims 1 and 4, wherein said first cascade gate has a cascade active region defined on said semiconductor substrate and said semiconductor device further comprises a conductor formed in contact with an end of said cascade gate active region, said conductor being connected to said first data node and is formed on a same wiring layer as said charge storage electrodes of said data storage capacitors.

Claim 16

The semiconductor memory device according to any one of claims 2, 3, 5, and 6, further comprising word lines each respectively connected to a gate of a corresponding one of said first MOS transistors for supplying signals to control the on/off switching of said first MOS transistors.

Claim 17

The semiconductor memory device according to any one of claims 1 to 3, 4 to 8, in which second electrodes of said data storage capacitors are connected to a common line.

Claim 18

The semiconductor memory device according to claim 13, in which said data storage capacitors have a common plate electrode which is supplied with a predetermined capacitor plate potential.

Claim 19

The semiconductor memory device according to any one of claims 1 to 3, 4 to 8, in which second electrodes of said data storage capacitors are connected to separate signal lines.

Claim 20

The semiconductor memory device according to any one of claims 1 to 3, 4 to 8, in which capacitance values of said data storage capacitors have a predetermined relationship in accordance with a sequence in which data is read out from said data storage capacitors.

Claim 21

The semiconductor memory device according to claim 16, in which the predetermined relationship of said capacitance values is such that the capacitor whose data is output last in said sequence has a greater capacitance than the capacitor whose data is output first in said sequence.

Claim 22

The semiconductor memory device according to any one of claims 1 to 3, 5 to 8, in which said first data node is connected to a bit line or an input terminal of a sense amplifier of a memory cell array.

Claim 23

The semiconductor memory device according to claim 7 or 8, in which one of said first MOS transistors at an end of said cascade gate is selectively placed in the off state, and the remaining transistors of said first MOS transistors are switched on and off in a predetermined sequence.

Claim 24

The semiconductor memory device according to claim 7 or 8, in which said first node and said second node are connected together.

Claim 25

The semiconductor memory device according to any one of claims 1 to 3, 4 to 8, further comprising an additional dynamic memory cell unit including transistors equal in number to the number of transistors in said dynamic memory cell units, said transistors of said additional dynamic memory cell unit connected in series such that a first terminal of a first transistor in said transistor series is connected to a data node and a first terminal of each remaining transistor in said transistor series is connected to a second terminal of the immediately preceding transistor in said transistor series, wherein second electrodes of said data storage capacitors of one of said first dynamic memory cell units are connected to the second terminals of the transistors of said additional dynamic memory cell unit and gates of said MOS transistors of said additional dynamic memory cell unit being connected to gates of said first MOS transistors of said one of said dynamic memory cell units, respectively.

Claim 26

The semiconductor memory device according to any one of claims 1 to 3, in which the number of said first MOS transistors connected in cascade is four, and the number of said data storage capacitors in each of said dynamic memory cell units is four.

Claim 27

The semiconductor memory device according to claim 7, in which the number of said first MOS transistors connected in cascade is five, and the number of said data storage capacitors is four.

Claim 28

A semiconductor memory device, comprising: memory cells comprising a plurality of transistors connected in series between first and second data nodes and arranged to extend linearly in a first direction on a major surface of a body of semiconductor material, said plurality of transistors including an isolation transistor, at least two transistors arranged in a first transistor series between said first data node and a first terminal of said isolation transistor, and at least two transistors arranged in a second transistor series between said second data node and a second terminal of said isolation transistor; gate lines connected to gates of said plurality of transistors; driving means for driving said gate lines, said driving means driving the gate line connected to said isolation transistor to maintain said isolation transistor in an OFF state and for driving the gate lines connected to the transistors in said first and second transistor series, while said isolation transistor is maintained in the OFF state, to switch said transistors in said first and second transistor series ON and OFF, whereby said isolation transistor electrically isolates said transistors in said first transistor series from said transistors in said second transistor series.

Claim 29

A semiconductor memory device, comprising: memory cells comprising a plurality of transistors connected in series between first and second data nodes and arranged to extend linearly in a first direction on a major surface of a body of semiconductor material, said plurality of transistors including an isolation transistor, at least two transistors arranged in a first transistor series between said first data node and a first terminal of said isolation transistor, and at least two transistors arranged in a second transistor series between said second data node and a second terminal of said isolation transistor; gate lines connected to gates of said plurality of transistors; driving means for driving said gate lines, said driving means driving the gate line connected to said isolation transistor to maintain said isolation transistor in an OFF state and for driving the gate lines connected to the transistors in said first and second transistor series, while said isolation transistor is maintained in the OFF state, to switch said transistors in said first and second transistor series ON and OFF, whereby said isolation transistor electrically isolates said transistors in said first transistor series from said transistors in said second transistor series.

Claim 30

The semiconductor memory device according to claim 24, wherein said transistors in said first transistor series are arranged such that a first terminal of a first transistor in said first transistor series is connected to said first data node, the first terminal of each remaining transistor in said first transistor series is connected to a second terminal of the immediately preceding transistor in said first transistor series, and said second terminal of a last transistor in said first transistor series is connected to said first terminal of said isolation transistor, and said transistors in said second transistor series are arranged such that a first terminal of a first transistor in said second transistor series is connected to said second data node, the first terminal of each remaining transistor in said second transistor series is connected to a second terminal of the immediately preceding transistor in said second transistor series, and said second terminal of a last transistor in said second transistor series is connected to said second terminal of said isolation transistor, said memory cells further comprising: data storage capacitors each having a first electrode respectively connected to the second terminal of a corresponding one of said transistors in said first and second transistor series.

Claim 31

The semiconductor memory device according to claim 25, further comprising: a bit line connected to said first and second data nodes, and wherein said driving means drives said gate lines, while said isolation transistor is maintained OFF, to read data from said data storage capacitors of said memory cells to said bit line and to write data from said bit line to said data storage capacitors of said memory cells.

Claim 32

The semiconductor memory device according to claim 26, further comprising: a precharge circuit for precharging said bit line.

Claim 33

The semiconductor memory device according to claim 26, further comprising: a sense amplifier for sensing and amplifying a potential on said bit line.

Claim 34

The semiconductor memory device according to claim 25, further comprising: a capacitor line to which a second electrode of each of said data storage capacitors is connected.

Claim 35

The semiconductor memory device according to claim 25, further comprising: capacitor lines each respectively coupled to a second electrode of a corresponding one of said data storage capacitors.

Claim 36

The semiconductor memory device according to claim 24, wherein said isolation transistor comprises an N-channel enhancement MOS transistor.

Claim 37

The semiconductor memory device according to claim 24, wherein said isolation transistor has a size different than a size of the transistors in said first and second transistor series.

Claim 38

The semiconductor memory device according to claim 24, further comprising: a first conductor contacting the first terminal of said first transistor in said first transistor series and electrically connecting said first terminal of said first transistor in said first transistor series to said first data node; and a second conductor contacting the first terminal of said first transistor in said second transistor series and electrically connecting said first terminal of said first transistor in said second transistor series to said second data node.

Claim 39

A semiconductor memory device, comprising: a circuit unit formed on a major surface of a body of semiconductor material comprising: at least two transistors connected in series such that a first terminal of a first transistor in said transistor series is connected to a first data node and a first terminal of each remaining transistor in said transistor series is connected to a second terminal of the immediately preceding transistor in said transistor series; and data storage capacitors each having a storage electrode respectively connected to the second terminal of a corresponding one of said transistors, an insulating film, and a plate electrode; a conductor contacting the first terminal of said first transistor in said transistor series and electrically connecting said first terminal of said first transistor in said transistor series to said first data node.

Claim 40

A semiconductor memory device, comprising: a circuit unit formed on a major surface of a body of semiconductor material comprising: at least two transistors connected in series such that a first terminal of a first transistor in said transistor series is connected to a first data node and a first terminal of each remaining transistor in said transistor series is connected to a second terminal of the immediately preceding transistor in said transistor series; and data storage capacitors each having a storage electrode respectively connected to the second terminal of a corresponding one of said transistors, an insulating film, and a plate electrode; a conductor contacting the first terminal of said first transistor in said transistor series and electrically connecting said first terminal of said first transistor in said transistor series to said first data node.

Claim 41

A semiconductor memory device, comprising: a first circuit unit formed on a major surface of a body of semiconductor material comprising: at least two transistors arranged to extend linearly in a first direction along the major surface of said semiconductor body and connected in a first transistor series such that a first terminal of a first transistor in said first transistor series is connected to a first data node and a first terminal of each remaining transistor in said first transistor series is connected to a second terminal of the immediately preceding transistor in said first transistor series; and first data storage capacitors each having a first terminal respectively connected to the second terminal of a corresponding one of said transistors in said first transistor series; a second circuit unit formed on said major surface of said semiconductor body and spaced from said first circuit unit in a second direction perpendicular to said first direction, said second circuit unit comprising: at least two transistors arranged to extend linearly in the first direction along the major surface of said semiconductor body and connected in a second transistor series such that a first terminal of a first transistor in said second transistor series is connected to a first data node and a first terminal of each remaining transistor in said second transistor series is connected to a second terminal of the immediately preceding transistor in said second transistor series; and second data storage capacitors each having a first terminal respectively connected to the second terminal of a corresponding one of said transistors in said second transistor series; means for electrically isolating said first circuit unit from said second circuit unit; and a bit line connected to the first terminal of the first transistor in said first transistor series and arranged in the space between said first and second circuit unit to extend in the first direction along the major surface of said semiconductor body.

Claim 42

A semiconductor memory device, comprising: a first circuit unit formed on a major surface of a body of semiconductor material comprising: at least two transistors arranged to extend linearly in a first direction along the major surface of said semiconductor body and connected in a first transistor series such that a first terminal of a first transistor in said first transistor series is connected to a first data node and a first terminal of each remaining transistor in said first transistor series is connected to a second terminal of the immediately preceding transistor in said first transistor series; and first data storage capacitors each having a first terminal respectively connected to the second terminal of a corresponding one of said transistors in said first transistor series; a second circuit unit formed on said major surface of said semiconductor body and spaced from said first circuit unit in a second direction perpendicular to said first direction, said second circuit unit comprising: at least two transistors arranged to extend linearly in the first direction along the major surface of said semiconductor body and connected in a second transistor series such that a first terminal of a first transistor in said second transistor series is connected to a first data node and a first terminal of each remaining transistor in said second transistor series is connected to a second terminal of the immediately preceding transistor in said second transistor series; and second data storage capacitors each having a first terminal respectively connected to the second terminal of a corresponding one of said transistors in said second transistor series; means for electrically isolating said first circuit unit from said second circuit unit; and a bit line connected to the first terminal of the first transistor in said first transistor series and arranged in the space between said first and second circuit unit to extend in the first direction along the major surface of said semiconductor body.

Claim 43

The semiconductor memory device according to claim 35, wherein said means for electrically isolating comprises a field oxide film.

Claim 44

The semiconductor memory device according to claim 35, wherein said means for electrically isolating comprises: an impurity region formed in the major surface of said semiconductor body in the space between said first and second circuit units; and a polysilicon layer insulatively spaced from said impurity region and supplied with a potential suitable for electrically isolating said first and second circuit units from each other.

Claim 45

The semiconductor memory device according to claim 25, further comprising: a first conductor contacting the first terminal of said first transistor in said first transistor series and electrically connecting said first terminal of said first transistor in said first transistor series to said first data node; and a second conductor contacting the first terminal of said first transistor in said second transistor series and electrically connecting said first terminal of said first transistor in said second transistor series to said second data node.

Claim 46

The semiconductor memory device according to claim 38, wherein said first and second conductors are formed in the same pattern at the same level above said semiconductor substrate as the first electrodes of said data storage capacitors.