EP0169460A2
Expired / Lapsed
EP
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Dynamic memory array with segmented and quasi-folded bit lines
Assignee: Texas Instruments Inc
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Filing: 1985-07-12
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Granted: —
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Expires: 2005-07-12
Abstract
Abstract A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells, with a differential sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects one of two segments to be connected to one of two bit lines. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate. Also, instead of being interleaved one-for-one, the word lines for cells to be connected to the two bit lines are in groups, one group for each segment line; the groups are interleaved. The combined segment line and bit line capacitance has a more favorable ratio to the storage capacitance, compared to the one-for-one interleaved layout.
Inventors
- 👤 David J. Mcelroy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 03:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/409; G11C11/4097
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
117 words
A semiconductor memory device comprising: an array of rows and columns of memory cells, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said rows of cells, each cell including storage means coupled to a source-to-drain path of said access transistor, a plurality of bit lines extending along said columns of cells perpendicular to said word lines, a plurality of bit line segments for each of said bit lines, said segments extending parallel to said bit lines, the source-to-drain paths of said access transistors being connected to said segments, and control means selectively connecting said segments to a bit line in response to an address,
Claim 2
Dependent Claim
117 words
A semiconductor memory device comprising: an array of rows and columns of memory cells, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said rows of cells, each cell including storage means coupled to a source-to-drain path of said access transistor, a plurality of bit lines extending along said columns of cells perpendicular to said word lines, a plurality of bit line segments for each of said bit lines, said segments extending parallel to said bit lines, the source-to-drain paths of said access transistors being connected to said segments, and control means selectively connecting said segments to a bit line in response to an address,
Claim 3
Dependent Claim
30 words
A device according to claim 1 including a plurality of differential sense amplifiers, each sense amplifier having two inputs, each input coupled to a different one of said bit lines.
Claim 4
Dependent Claim
37 words
A device according to claim 2 including row addressing means for receiving said address and activating said control means; said row addressing means also activating a selected one of said word lines in response to said address.
Claim 5
Dependent Claim
24 words
A device according to claim 2 wherein the capacitance per unit length of said bit lines is much less than that of said segments.
Claim 6
Dependent Claim
20 words
A device according to claim 1 wherein there are a plurality of said cells connected to each of said segments.
Claim 7
Dependent Claim
23 words
A device according to claim 5 wherein there is at least eight segments per bit line and at least eight cells per segment.
Claim 8
Dependent Claim
149 words
A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in a face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell, a plurality of bit lines extending along said face above said word lines and over said columns of cells perpendicular to said word lines, a plurality of bit line segments for each of said bit lines, said segments extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and control means for each of said segments for selectively connecting each said segment to a bit line.
Claim 9
Dependent Claim
149 words
A semiconductor dynamic memory device comprising: an array of rows and columns of one-transistor memory cells formed in a face of a semiconductor body, each cell including an access transistor having a gate connected to one of a plurality of parallel word lines extending along said face over said rows of cells, each cell including a storage capacitor coupled to a source-to-drain path of said access transistor of the cell, a plurality of bit lines extending along said face above said word lines and over said columns of cells perpendicular to said word lines, a plurality of bit line segments for each of said bit lines, said segments extending parallel to said bit lines, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and control means for each of said segments for selectively connecting each said segment to a bit line.
Claim 10
Dependent Claim
41 words
A device according to claim 7 including a plurality of differential sense amplifiers, one of said sense amplifiers for each column, each sense amplifier having two inputs, each input coupled to a different one of a pair of said bit lines.
Claim 11
Dependent Claim
43 words
A device according to claim 8 including row addressing means for receiving an address and selectively activating said control means in response to said address; said row addressing means also activating a selected one of said word lines in response to said address.
Claim 12
Dependent Claim
24 words
A device according to claim 7 wherein the capacitance per unit length of said bit lines is much less than that of said segments.
Claim 13
Dependent Claim
95 words
In a semiconductor memory device: a plurality of memory cells in a column, each cell including an access transistor having a gate, each cell including storage means coupled to a source-to-drain path of said access transistor, at least one bit line extending along said column of cells, a plurality of bit line segments for said bit lines, each of said segments extending parallel to said bit line, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and control means selectively connecting said segments to said bit line.
Claim 14
Dependent Claim
95 words
In a semiconductor memory device: a plurality of memory cells in a column, each cell including an access transistor having a gate, each cell including storage means coupled to a source-to-drain path of said access transistor, at least one bit line extending along said column of cells, a plurality of bit line segments for said bit lines, each of said segments extending parallel to said bit line, the source-to-drain paths of a plurality of said access transistors being connected to each of said segments, and control means selectively connecting said segments to said bit line.
Claim 15
Dependent Claim
32 words
A device according to claim 11 including at least two of said bit lines, and a differential sense amplifier having two inputs, each input coupled to one of said two bit lines.
Claim 16
Dependent Claim
35 words
A device according to claim 11 including addressing means for receiving an address and selectively activating said control means; said addressing means also activating a selected one of said gates in response to said address.
Claim 17
Dependent Claim
24 words
A device according to claim 11 wherein the capacitance per unit length of said bit line is much less than that of said segments.
Claim 18
Dependent Claim
25 words
A device according to claim 11 wherein there are at least eight of said segments and at least eight of said cells for each segment.
Claim 19
Dependent Claim
147 words
A semiconductor memory device comprising: an array of rows and columns of memory cells, each column having a pair of balanced bit lines connected to memory cells of the columns, each memory cell in a row having a control input connected to a row line for the row of cells, a plurality of differential sense amplifiers, each sense amplifier having a pair of inputs coupled to said pair of bit lines of a different one of said columns, said pair of bit lines both being physically located on the same side of the sense amplifier in a folded bit line configuration, said memory cells in a column being partitioned in a plurality of groups of adjacent cells, all of the cells in each group being coupled to the same bit line, the cells in alternate groups being connected to alternate ones of a pair of bit lines.
Claim 20
Dependent Claim
147 words
A semiconductor memory device comprising: an array of rows and columns of memory cells, each column having a pair of balanced bit lines connected to memory cells of the columns, each memory cell in a row having a control input connected to a row line for the row of cells, a plurality of differential sense amplifiers, each sense amplifier having a pair of inputs coupled to said pair of bit lines of a different one of said columns, said pair of bit lines both being physically located on the same side of the sense amplifier in a folded bit line configuration, said memory cells in a column being partitioned in a plurality of groups of adjacent cells, all of the cells in each group being coupled to the same bit line, the cells in alternate groups being connected to alternate ones of a pair of bit lines.
Claim 21
Dependent Claim
171 words
A semiconductor dynamic read/write memory device comprising: an array of rows and columns of one-transistor read/write memory cells formed in a face of a semiconductor body each column having a pair of balanced bit lines connected to memory cells of the columns, each memory cell in a row having an access transistor with a gate connected to a row line for the row of cells, a plurality of differential sense amplifiers, each sense amplifier having a pair of inputs coupled to said pair of bit lines of a different one of said columns, said pair of bit lines both being physically located on the same side of the sense amplifier in a folded bit line configuration, said memory cells in a column being positioned in an even number of groups of adjacent cells, the source-to-drain paths of the access transistors of all of the cells in each group being coupled to the same bit line, the cells in alternate groups being connected to alternate ones of a pair of bit lines.
Claim 22
Dependent Claim
171 words
A semiconductor dynamic read/write memory device comprising: an array of rows and columns of one-transistor read/write memory cells formed in a face of a semiconductor body each column having a pair of balanced bit lines connected to memory cells of the columns, each memory cell in a row having an access transistor with a gate connected to a row line for the row of cells, a plurality of differential sense amplifiers, each sense amplifier having a pair of inputs coupled to said pair of bit lines of a different one of said columns, said pair of bit lines both being physically located on the same side of the sense amplifier in a folded bit line configuration, said memory cells in a column being positioned in an even number of groups of adjacent cells, the source-to-drain paths of the access transistors of all of the cells in each group being coupled to the same bit line, the cells in alternate groups being connected to alternate ones of a pair of bit lines.
References Cited (Backward Citations)
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