US4593382A
Expired / Lapsed
US
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MOS dynamic memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1982-09-16
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Granted: 1986-06-03
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Expires: 2002-09-16
Abstract
Abstract An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.
Inventors
- 👤 Kazuyasu Fujishima
- 👤 Kazuhiro Shimotori
- 👤 Hideyuki Ozaki
- 👤 Takao Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
143 words
In an MOS dynamic memory device of the single transistor type including a matrix of memory cells (1) arranged in rows and columns, each cell comprising a transistor and a memory capacitor, a plurality of word lines (5) arranged in one of a row or column direction of the matrix, and a plurality of bit lines (4) arranged orthogonal to the word lines, the improvement comprising: a cell plate voltage control circuit (13), said voltage control circuit comprising at least one transistor connected between cell plates (8) of the memory cells in each column of memory cells and a control signal terminal connected to said cell plate voltage control circuit and being adapted to discharge voltages applied upon a cell plate to said control signal terminal for re-charging the cell plate within a time period during which the word lines are selectively driven.
Claim 2
Dependent Claim
143 words
In an MOS dynamic memory device of the single transistor type including a matrix of memory cells (1) arranged in rows and columns, each cell comprising a transistor and a memory capacitor, a plurality of word lines (5) arranged in one of a row or column direction of the matrix, and a plurality of bit lines (4) arranged orthogonal to the word lines, the improvement comprising: a cell plate voltage control circuit (13), said voltage control circuit comprising at least one transistor connected between cell plates (8) of the memory cells in each column of memory cells and a control signal terminal connected to said cell plate voltage control circuit and being adapted to discharge voltages applied upon a cell plate to said control signal terminal for re-charging the cell plate within a time period during which the word lines are selectively driven.
Claim 3
Dependent Claim
29 words
An MOS dynamic memory device as claimed in claim 1, wherein said cell plate voltage control circuit is arranged at a terminal portion of each of the word lines.
Claim 4
Dependent Claim
22 words
An MOS dynamic memory device as claimed in claim 1, wherein said cell plate voltage control circuit comprises three enhancement type transistors.
Claim 5
Dependent Claim
27 words
An MOS dynamic memory device as claimed in claim 1, wherein said cell plate voltage control circuit comprises a depletion type transistor and an enhancement type transistor.
Claim 6
Dependent Claim
26 words
An MOS dynamic memory device as claimed in claim 1, wherein said cell plate voltage control circuit comprises a resistor element and an enhancement type transistor.
Claim 7
Dependent Claim
130 words
An MOS dynamic memory device, comprising: a matrix of memory cells (1) arranged in rows and columns, a plurality of word lines (5) arranged in a column direction of the matrix and individually coupled to each of the memory cells in an associated column, means (17, 18) for driving said word lines, a plurality of bit lines (4) arranged orthogonal to said word lines and individually coupled to each of the memory cells in an associated row, a plurality of memory capacitor cell plates (8) individually associated with the memory cells and connected in columns parallel to said word lines, and means (13) for recharging a selected cell plate after a discharge thereof within a time period during which a word line associated with said selected cell plate remains driven.
Claim 8
Dependent Claim
130 words
An MOS dynamic memory device, comprising: a matrix of memory cells (1) arranged in rows and columns, a plurality of word lines (5) arranged in a column direction of the matrix and individually coupled to each of the memory cells in an associated column, means (17, 18) for driving said word lines, a plurality of bit lines (4) arranged orthogonal to said word lines and individually coupled to each of the memory cells in an associated row, a plurality of memory capacitor cell plates (8) individually associated with the memory cells and connected in columns parallel to said word lines, and means (13) for recharging a selected cell plate after a discharge thereof within a time period during which a word line associated with said selected cell plate remains driven.
Claim 9
Dependent Claim
39 words
An MOS dynamic memory device as claimed in claim 6, wherein said recharging means comprises a cell plate voltage control circuit containing at least one transistor, one said circuit being arranged at a terminus of each said word line.
Claim 10
Dependent Claim
33 words
An MOS dynamic memory device as claimed in claim 7, including means for triggering said at least one transistor, for applying a voltage to a cell plate connected with said voltage control circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |