Dynamic semiconductor memory device

Claim 2

A semiconductor memory device operatively connected to receive address signals and clock signals, said device comprising: first and second power supplies, the potential of said second power supply being lower than said first power supply potential; a plurality of word lines; a plurality of power supply lines; a plurality of pairs of bit lines; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said pairs of bit lines; a plurality of memory cells, each comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance and an electrode connected to the source of said transistor and another electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to said power supply lines and to said word lines, for selectively supplying a clock signal to corresponding of said power supply lines in response to said address signals and after the potential of said corresponding word line rises and before the potential of said corresponding word line falls, the potential of said clock signal falls and after that, rises.

Claim 3

A device as set forth in claim 1, wherein said clock signal falls from the potential of said first power supply to the potential of said second power supply and after that, rises from the potential of said second power supply to the potential of said first power supply.

Claim 4

A device as set forth in claim 1 or 2, further comprising: two dummy word lines; and a plurality of dummy memory cells, respective of said dummy cells connected to a corresponding one of said bit lines, to a corresponding one of said two dummy word lines and to said second power supply.

Claim 5

A device as set forth in claim 3, wherein each of said dummy memory cells comprises: a first dummy transistor having a drain connected to said corresponding one of said bit lines, a gate connected to said corresponding one of said two dummy word lines; a dummy capacitor having predetermined capacitance and a first electrode connected to a source of said first dummy transistor and a second electrode connected to receive said second power supply; and a second dummy transistor having a drain and a source connected to the first electrode and to the second electrode, respectively, and a gate for receiving a reset signal.

Claim 6

A device as set forth in claim 4, wherein the capacitance of the dummy capacitor of said dummy memory cells is the same as that of the capacitor of said memory cells.

Claim 7

The device as set forth in claim 3, wherein each of said sense amplifiers comprises means for latching data from said corresponding pair of said pairs of bit lines, and wherein said fall and rise of said clock signal occurs after said latching.

Claim 8

A dynamic semiconductor memory device operatively connected to receive address signals and clock signals, a first power supply voltage, and a second power supply voltage lower than said first power supply voltage, comprising: a plurality of word lines, each having a potential; a plurality of power supply lines arranged parallel to said word lines; a plurality of bit line pairs, said bit line pairs and said word lines arranged in a matrix; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said bit line pairs, and comprising means for latching data from said corresponding pair of said pairs of bit lines; a plurality of memory cells arranged at cross points of said matrix, each of said memory cells comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance, having a first electrode connected to the source of said transistor and having a second electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to receive said clock signals and said address signals and operatively connected to said word lines and said power supply lines for providing a negative clock pulse to corresponding ones of said word lines and power supply lines responsive to corresponding ones of said address signals and of said clock signals, wherein said clock means comprises means for providing control signals responsive to said corresponding of said control signals and to said clock signals, for providing said negative clock pulse after the potential of at least one of said corresponding ones of said word lines rises and before said potential falls.

Claim 9

A dynamic semiconductor memory device operatively connected to receive address signals and clock signals, a first power supply voltage, and a second power supply voltage lower than said first power supply voltage, comprising: a plurality of word lines, each having a potential; a plurality of power supply lines arranged parallel to said word lines; a plurality of bit line pairs, said bit line pairs and said word lines arranged in a matrix; a plurality of sense amplifiers, respective of said sense amplifiers operatively connected between a corresponding pair of said bit line pairs, and comprising means for latching data from said corresponding pair of said pairs of bit lines; a plurality of memory cells arranged at cross points of said matrix, each of said memory cells comprising a transistor having a gate connected to a corresponding one of said word lines, a drain connected to a corresponding one of said bit lines, and a source, a capacitor having a predetermined capacitance, having a first electrode connected to the source of said transistor and having a second electrode connected to a corresponding one of said power supply lines; and clock means operatively connected to receive said clock signals and said address signals and operatively connected to said word lines and said power supply lines for providing a negative clock pulse to corresponding ones of said word lines and power supply lines responsive to corresponding ones of said address signals and of said clock signals, wherein said clock means comprises means for providing control signals responsive to said corresponding of said control signals and to said clock signals, for providing said negative clock pulse after the potential of at least one of said corresponding ones of said word lines rises and before said potential falls.