EP0398244A2
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EP
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Dynamic type random-acces memory
Assignee: Toshiba Corp
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Filing: 1990-05-15
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Granted: —
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Expires: 2010-05-15
Abstract
Abstract This invention discloses a dynamic type random-access memory which includes a bit line pair, a memory cell array including a plurality of memory cells (MC i ; i = 0 to 255), a bit line sense amplifier (NA, PA) which is enabled after data written in one of the plurality of memory cells (MC i ; i = 0 to 255) is read out onto the bit line pair, and a charge transfer circuit (NT₁, NT₂) which is connected between the bit line pair and sense nodes (SN, SN ) of the bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of the bit line sense amplifier (NA, PA) is started.
Inventors
- 👤 Takashi C/O Intellectual Property Div. Ohsawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 08:19
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/4091
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
147 words
A dynamic type random-access memory comprising: a bit line pair consisting of first and second bit lines (BL, BL ); a memory cell array including a plurality of memory cells (MC i ) connected to said bit line pair; a precharge circuit (PR) for precharging said bit line pair to a predetermined voltage at a predetermined timing; a bit line sense amplifier (NA, PA) which is enabled after data written in one of said plurality of memory cells (MC i ) is read out onto said bit line pair; and a charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) which is connected between said bit line pair and sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of said bit line sense amplifier (NA, PA) is started.
Claim 2
Dependent Claim
147 words
A dynamic type random-access memory comprising: a bit line pair consisting of first and second bit lines (BL, BL ); a memory cell array including a plurality of memory cells (MC i ) connected to said bit line pair; a precharge circuit (PR) for precharging said bit line pair to a predetermined voltage at a predetermined timing; a bit line sense amplifier (NA, PA) which is enabled after data written in one of said plurality of memory cells (MC i ) is read out onto said bit line pair; and a charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) which is connected between said bit line pair and sense nodes (SN, SN ) of said bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of said bit line sense amplifier (NA, PA) is started.
Claim 3
Dependent Claim
102 words
A memory according to claim 1, characterized in that an impedance of said charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) is changed when a potential difference between a first terminal of said bit line pair (BL, BL ) and a second terminal of said sense nodes (SN, SN ) is changed, said charge transfer circuit is turned off when a potential difference between a third terminal and one of the first and second terminals exceeds a predetermined value, and is controlled to be in an OFF state after said bit line sense amplifier (NA, PA) starts the sense amplification operation.
Claim 4
Dependent Claim
65 words
A memory according to claim 1, characterized in that said charge transfer circuit (NT₁, NT₂, PT₁, PT₂, S, D) comprises a field effect transistor, a source and a drain of which are connected to the first and second terminals, and a gate of which is connected to the third terminal, the gate being supplied with a charge transfer transistor drive signal from the third terminal.
Claim 5
Dependent Claim
77 words
A memory according to claim 3, characterized in that said field effect transistor comprises an n-channel MOS transistor (NT₁, NT₂) which is turned off when the charge transfer transistor drive signal supplied to the gate is decreased from a power source potential to an intermediate potential between the power source potential and a ground potential, and is turned on when the charge transfer transistor drive signal is increased from the intermediate potential to the power source potential.
Claim 6
Dependent Claim
75 words
A memory according to claim 3, characterized in that said field effect transistor comprises a p-channel MOS transistor (PT₁, PT₂) which is turned off when the charge transfer transistor drive signal supplied to the gate of increased from a ground potential to an intermediate potential between the ground potential and a power source potential, and is turned on when the charge transfer transistor drive signal is decreased from the intermediate potential to the ground potential.
Claim 7
Dependent Claim
34 words
A memory according to claim 1, characterized in that said charge transfer circuit (S, D) comprises a parallel circuit of a switching circuit (S) and a diode (D), and switching-controls said switching circuit (S).
References Cited (Backward Citations)
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