MOS type semiconductor device

Claim 1

An erasable programmable read-only memory device comprising: (a) a semiconductive substrate; (b) parallel bit lines disposed above said substrate; (c) parallel word lines disposed above said substrate to intersect said bit lines; (d) double gate field effect transistors disposed at intersections between said bit lines and said word lines and functioning as memory cells of said device, said transistors including two adjacent cell arrays each of which has a series-circuit of cell transistors for constituting a NAND cell structure, each of said cell transistors having an electrically floating gate and a control gate which is connected to a corresponding word line; (e) field effect transistors respectively provided for said cell arrays, each having a gate and functioning as a switching transistor for selectively coupling a cell array at opposite ends of said cell array to a corresponding one of said bit lines and a substrate potential, respectively, said switching transistors having a conductive layer formed to extend in parallel with said word line serving as a common control gate electrode thereof; (f) a heavily doped semiconductive inversion prevention layer disposed between said switching transistors, for suppressing interference between said switching transistors, said inversion prevention layer insulatively intersecting said common gate electrode with a front edge thereof being projected from a side end of said common electrode; and (g) said common gate electrode having a reduced width in an area of intersection with said inversion prevention layer, thereby increasing a substantial projection distance of said inversion prevention layer.