EP0157051A2
Expired / Lapsed
EP
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A semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-12-13
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Granted: —
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Expires: 2004-12-13
Abstract
Abstract In a MOS-dRAM formed by integrating memory cells each formed of an MOS capacitor (2) and an MOSFET (1), a D-type transistor with a threshold voltage lower than that of MOSFETs of peripheral circuits is used for the MOSFET (1) of each memory cell. Thus, a word line driver without a pull-up circuit can be used, permitting high-speed access of the MOS-dRAM.
Inventors
- 👤 Koji C/O Patent Division Sakui
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4085
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
226 words
A semiconductor memory device comprising: a semiconductor substrate; a memory array formed of a plurality of memory cells (Mij) arranged in the form of a matrix on the substrate, each said memory cell including a memory capacitor (2) and an MOSFET (1) whose source is connected to one end of the capacitor (2); a plurality of word lines (WLj) formed on the substrate each connected in common with the gates of the MOSFETs of a plurality of said memory cells arranged along each corresponding column of said memory array; a plurality of digit lines (DLi) formed on the substrate each connected in common with the drains of the MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array; and a word line driver formed on the substrate for selectively driving said plurality of word lines, characterized in that the MOSFET (1) of each said memory cell (Mij) has its channel region doped with impurities of the conductivity type opposite to that of the substrate, and that said word line driver supplies a selected word line with a first-polarity voltage to turn on the MOSFET of the memory cell connected to said selected word line, and the remaining nonselected word lines with a second-polarity voltage to keep the MOSFETs of the memory cells connected to the nonselected word lines off.
Claim 2
Dependent Claim
226 words
A semiconductor memory device comprising: a semiconductor substrate; a memory array formed of a plurality of memory cells (Mij) arranged in the form of a matrix on the substrate, each said memory cell including a memory capacitor (2) and an MOSFET (1) whose source is connected to one end of the capacitor (2); a plurality of word lines (WLj) formed on the substrate each connected in common with the gates of the MOSFETs of a plurality of said memory cells arranged along each corresponding column of said memory array; a plurality of digit lines (DLi) formed on the substrate each connected in common with the drains of the MOSFETs of a plurality of said memory cells arranged along each corresponding row of said memory array; and a word line driver formed on the substrate for selectively driving said plurality of word lines, characterized in that the MOSFET (1) of each said memory cell (Mij) has its channel region doped with impurities of the conductivity type opposite to that of the substrate, and that said word line driver supplies a selected word line with a first-polarity voltage to turn on the MOSFET of the memory cell connected to said selected word line, and the remaining nonselected word lines with a second-polarity voltage to keep the MOSFETs of the memory cells connected to the nonselected word lines off.
Claim 3
Dependent Claim
60 words
A semiconductor memory device according to claim 1, characterized in that said word line driver includes a decoder (12) adapted to deliver said first-polarity voltage to a selected output terminal designated by an internal address signal, and said second-polarity voltage to the remaining nonselected output terminals, and a clock generator (11) for controlling the operating timing of the decoder (12).
Claim 4
Dependent Claim
31 words
A semiconductor memory device according to claim 1, characterized in that the output voltage of a back-gate bias generator is used for said second-polarity output voltage of said word line driver.
Claim 5
Dependent Claim
44 words
A semiconductor memory device according to claim 1, characterized in that the relation: is established where Vth is the threshold voltage of the MOSFET (1) of each said memory cell (Mij) and V L is the second-polarity output voltage from said word line driver.
References Cited (Backward Citations)
No citation records indexed.
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