EP0273639A2
Expired / Lapsed
EP
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Semiconductor memory having multiple level storage structure
Assignee: Toshiba Corp
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Filing: 1987-12-15
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Granted: —
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Expires: 2007-12-15
Abstract
Abstract The invention provides a semiconductor memory having a plurality of memory cells (12) and a bit line (BL1) connected to the memory cells (12), characterised by: the bit line (BL1) being formed of a plurality of sub-bit lines (BL1 a-c), switch means (11) for interconnecting and disconnecting the sub-bit lines (BL1 a-c), reference potential means (13) for storing reference potentials, and sense amplifier means (SA1-3) for comparing the output of an addressed memory cell (12) with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.
Inventors
- 👤 Thoru Patent Division Toshiba Corp. Furuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:52
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/18; G11C11/56; G11C11/565; G11C16/00; G11C16/02; G11C16/06; G11C16/24
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
90 words
A semiconductor memory having a plurality of memory cells (12) and a bit line (BL1) connected to the memory cells (12), characterised by: the bit line (BL1) being formed of a plurality of sub-bit lines (BL1 a-c), switch means (11) for interconnecting and disconnecting the sub-bit lines (BL1 a-c), reference potential means (13) for storing reference potentials, and sense amplifier means (SA1-3) for comparing the output of an addressed memory cell (12) with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.
Claim 2
Dependent Claim
90 words
A semiconductor memory having a plurality of memory cells (12) and a bit line (BL1) connected to the memory cells (12), characterised by: the bit line (BL1) being formed of a plurality of sub-bit lines (BL1 a-c), switch means (11) for interconnecting and disconnecting the sub-bit lines (BL1 a-c), reference potential means (13) for storing reference potentials, and sense amplifier means (SA1-3) for comparing the output of an addressed memory cell (12) with the reference potentials, whereby the memory is capable of storing n-valued data using n different storage potentials.
Claim 3
Dependent Claim
29 words
A semiconductor memory as claimed in claim 1, further characterised in that each of the memory cells (12) stores data for m bits where n equals 2 m .
Claim 4
Dependent Claim
31 words
A semiconductor memory as claimed in claim 1 or 2, further characterised in that each of the memory cells (12) comprises a data storage capacitor (31) and a selection transistor (32).
Claim 5
Dependent Claim
28 words
A semiconductor memory as claimed in any preceding claim, further characterised in that the switch means (11) comprises respective switching elements which interconnected the sub-bit lines (BL1 a-c).
Claim 6
Dependent Claim
25 words
A semiconductor memory as claimed in any preceding claim, further characterised in that the reference potential means (13) comprises a plurality of dummy memory cells.
Claim 7
Dependent Claim
27 words
A semiconductor memory as claimed in claim 5, further characterised in that each dummy memory cell comprises a data storage capacitor (31) and a selection transistor (32).
Claim 8
Dependent Claim
62 words
A semiconductor memory as claimed in any preceding claim, further characterised by data detection means (41-50) connected to the sense amplifier means (SA1-3) for outputting data as a data level which is the (t + 1)th of the n-valued data when the potential of t sub-bit lines (0 ≤ ℓ ≦ (n-1)) are each at a higher level than respective reference potentials.
Claim 9
Dependent Claim
61 words
A semiconductor memory as claimed in any preceding claim, further characterised by data write means (61-68) connected to the sense amplifier means (SA1-3) for writing data to the memory cells (12) by setting the potential of t sub-bit lines (0 5 t 5 (n-1)) to a logic high level and the remainder of the sub-bit lines to a logic low level.
Claim 10
Dependent Claim
50 words
A semiconductor memory as claimed in claim 4, further characterised in that the switching elements (11) are formed of N channel MOS transistors, with the gate of the N channel MOS transistors being operably supplied with a higher potential than the high level potential of the sub-bit lines (BL1 a-c).
Claim 11
Dependent Claim
50 words
A semiconductor memory as claimed in claim 4, further characterised in that the switching elements (11) are formed of P channel MOS transistors with the gate of the P channel MOS transistors being operably supplied with a lower potential than the low level potential of the sub-bit lines (BL1 a-c).
Claim 12
Dependent Claim
22 words
A semiconductor memory as claimed in claim 4, further characterised in that the switching elements (11) are formed of CMOS transfer gates.
Claim 13
Dependent Claim
40 words
A semiconductor memory as claimed in claim 6, further characterised in that the value of the capacitor (31) of the dummy memory cells (13) is set tote substantially 1/(n-1) of the value of capacitor (31) of the memory cells (12).
Claim 14
Dependent Claim
47 words
A semiconductor memory as claimed in claim 5, further characterised in that the dummy memory cells (13) each produce a potential which is substantially (k - 0.5)/(n-1) of the maximum storage potential of the memory cells (12) where K (1 ≦ k ≦ (n-1)) is an integer.
References Cited (Backward Citations)
No citation records indexed.
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