Low threshold voltage epitaxial DMOS technology

Claim 2

A vertical power MOS transistor structure, comprising: a substrate layer; a relatively heavily doped epitaxial layer disposed directly on said substrate layer, said relatively heavily doped epitaxial layer being of a first conductivity type and having a redistribution layer and another layer disposed over said redistribution layer, said another layer having a substantially constant first doping concentration of said first conductivity type, said relatively heavily doped epitaxial layer having been grown with said first doping concentration; a relatively lightly doped epitaxial layer disposed directly on said relatively heavily doped epitaxial layer, said relatively lightly doped epitaxial layer being of said first conductivity type, said relatively lightly doped epitaxial layer having an upper surface, said relatively lightly doped epitaxial layer having a second doping concentration of said first conductivity type, said second doping concentration being smaller than said first doping concentration, said relatively lightly doped epitaxial layer having been grown with said second doping concentration; a body region extending through said relatively lightly doped epitaxial layer from said upper surface and into said relatively heavily doped epitaxial layer, said body region being of a second conductivity type opposite said first conductivity type; a source region disposed in said body region to define a channel region in said relatively lightly doped epitaxial layer at said upper surface, said source region being of said first conductivity type; a gate insulating layer disposed directly on said upper surface; and a gate, disposed at least partly over said channel region and being insulated from said channel region by said gate insulating layer.

Claim 3

The vertical power MOS transistor structure of claim 1, wherein said body region has a doping concentration of dopants of said second conductivity type, said doping concentration of said body region being substantially greater than said second doping concentration of said relatively lightly doped epitaxial layer.

Claim 4

The vertical power MOS transistor structure of claim 2, wherein said doping concentration of said body region is substantially equal to said first doping concentration of said another layer of said relatively heavily doped epitaxial layer.

Claim 5

The vertical power MOS transistor structure of claim 1, wherein a portion of said source region abuts said channel region and wherein said portion of said source region is disposed only within said relatively lightly doped epitaxial layer.

Claim 6

The vertical power MOS transistor structure of claim 4, wherein said source region is disposed only with said relatively lightly doped epitaxial layer.

Claim 7

The vertical power MOS transistor structure of claim 1, wherein a portion of said source region extends downward into said relatively heavily doped epitaxial layer.

Claim 8

A doubly diffused vertical power MOS transistor structure, comprising: a substrate layer; a first epitaxial silicon layer disposed directly on said substrate layer and having a redistribution layer and another layer disposed over said redistribution layer, said another layer having a substantially constant first doping concentration of N type dopants, said first epitaxial silicon layer being grown having said first doping concentration of N type dopants; a second epitaxial silicon layer disposed directly on said first epitaxial layer, said second epitaxial silicon layer being grown having a second doping concentration of N type dopants, said second epitaxial layer having an upper surface, said first doping concentration being greater than said second doping concentration; a P type body region extending from said upper surface through said second epitaxial silicon layer and into said first epitaxial silicon layer to define an epitaxial silicon region of said first epitaxial silicon layer, said P type body region defining a first lateral outer perimeter of said P type body region and defining a second lateral outer perimeter of said P type body region, said first and second lateral outer perimeters being disposed in respective lateral planes parallel to each other, said lateral plane containing said first lateral outer perimeter being disposed farther from said upper surface than said second lateral outer perimeter, said first and second planes being substantially parallel to said upper surface, said second lateral outer perimeter having a greater outer circumference than said first lateral outer perimeter, said first and second lateral outer perimeters both being disposed in said second epitaxial layer; an N type source region disposed in said body region and being disposed entirely within said second epitaxial silicon layer, said N type source region defining a minimum distance between said N type source region and said epitaxial silicon region of said first epitaxial silicon layer, said minimum distance extending in a direction somewhat laterally away from said N type source region; a gate insulating layer disposed directly on said upper surface; and a gate disposed at least partly over said gate insulating layer.

Claim 9

A doubly diffused vertical power MOS transistor structure, comprising: a substrate layer; a first epitaxial silicon layer disposed directly on said substrate layer and having a redistribution layer and another layer disposed over said redistribution layer, said another layer having a substantially constant first doping concentration of N type dopants, said first epitaxial silicon layer being grown having said first doping concentration of N type dopants; a second epitaxial silicon layer disposed directly on said first epitaxial layer, said second epitaxial silicon layer being grown having a second doping concentration of N type dopants, said second epitaxial layer having an upper surface, said first doping concentration being greater than said second doping concentration; a P type body region extending from said upper surface through said second epitaxial silicon layer and into said first epitaxial silicon layer to define an epitaxial silicon region of said first epitaxial silicon layer, said P type body region defining a first lateral outer perimeter of said P type body region and defining a second lateral outer perimeter of said P type body region, said first and second lateral outer perimeters being disposed in respective lateral planes parallel to each other, said lateral plane containing said first lateral outer perimeter being disposed farther from said upper surface than said second lateral outer perimeter, said first and second planes being substantially parallel to said upper surface, said second lateral outer perimeter having a greater outer circumference than said first lateral outer perimeter, said first and second lateral outer perimeters both being disposed in said second epitaxial layer; an N type source region disposed in said body region and being disposed entirely within said second epitaxial silicon layer, said N type source region defining a minimum distance between said N type source region and said epitaxial silicon region of said first epitaxial silicon layer, said minimum distance extending in a direction somewhat laterally away from said N type source region; a gate insulating layer disposed directly on said upper surface; and a gate disposed at least partly over said gate insulating layer.