Vertical MOSFET having a proof structure against puncture due to breakdown

Claim 2

An MOS transistor comprising: a drain region having a low resistivity region of a first conductivity type, a redistributed region of said first conductivity type above said low resistivity region, and a high resistivity region of the first conductivity type above said redistributed region; a well region of a second conductivity type having a first well portion with a curved section in contact with said high resistivity region and having a second well portion, said second well portion and being narrower than said first well portion, said second well portion extending below said first well portion into contact with said redistributed region; a channel region of the second conductivity type contained in said first well portion; a source region of the first conductivity type adjacent to the channel region of said well region; a gate electrode formed above the channel region on an insulator layer; a source electrode formed in contact with the source region and in contact with the upper surface of the second well portion of the well region, and a drain electrode formed on the bottom surface of the low resistivity region.

Claim 3

The MOS transistor of claim 1, wherein said drain region comprises a drain substrate and an epitaxial layer on said drain substrate, said redistributed layer being diffused from the drain substrate into said epitaxial layer.

Claim 4

The MOS transistor of claim 1, wherein said first well portion has a lower surface above said redistributed region.

Claim 5

The MOS transistor of claim 1, wherein said contact of said second well portion and said source electrode is made through a low resistivity contact portion of said second well portion.

Claim 6

The MOS transistor of claim 4, wherein said contact portion extends below said source region.

Claim 7

The MOS transistor of claim 5, wherein said contact portion is elongated laterally along a bottom surface of said source region.

Claim 8

An MOS transistor comprising: a drain region having a low resistivity region of a first conductivity type, a redistributed region of said first conductivity type above said low resistivity region and a high resistivity region of the first conducitivty typ above said redistributed region, said redistributed region having an upper surface; a well region of a second conductivity type having a portion extending into a portion of said redistributed region, said portion of said well region having an upper surface and having a wide lower surface below said upper surface of said redistributed region, said resistivity of said portion of said well region being approximately the same as that of said portion of said redistributed region; a channel region of the second conductivity type contained in said well region; a source region of the first conductivity type adjacent to the channel region; a gate electrode formed above the channel region on an insulator layer; a source electrode formed in contact with the source region and the upper surface of said portion of the well region, and a drain electrode formed on a bottom surface of the low resistivity region.

Claim 9

An MOS transistor comprising: a drain region having a low resistivity region of a first conductivity type, a redistributed region of said first conductivity type above said low resistivity region and a high resistivity region of the first conducitivty typ above said redistributed region, said redistributed region having an upper surface; a well region of a second conductivity type having a portion extending into a portion of said redistributed region, said portion of said well region having an upper surface and having a wide lower surface below said upper surface of said redistributed region, said resistivity of said portion of said well region being approximately the same as that of said portion of said redistributed region; a channel region of the second conductivity type contained in said well region; a source region of the first conductivity type adjacent to the channel region; a gate electrode formed above the channel region on an insulator layer; a source electrode formed in contact with the source region and the upper surface of said portion of the well region, and a drain electrode formed on a bottom surface of the low resistivity region.