US5466629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating ferroelectric integrated circuit
Assignee: Symetrix Corp
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Filing: 1995-02-03
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Granted: 1995-11-14
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Expires: 2015-02-03
Abstract
Abstract An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.
Inventors
- 👤 Takashi Mihara
- 👤 Hiroyuki Yoshimori
- 👤 Hitoshi Watanabe
- 👤 Larry D. McMillan
- 👤 Carlos P. de Araujo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/682
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
114 words
A method of fabricating an integrated circuit comprising: providing a semiconducting wafer including a semiconducting substrate; forming a bottom capacitor electrode, a ferroelectric layer, and a top capacitor electrode without intervening photo-mask steps; patterning said ferroelectric capacitor circuit to provide an edge having an outer bottom capacitor electrode portion, an outer ferroelectric layer portion, and a top capacitor electrode portion, said bottom capacitor electrode portion extending outwardly beyond said top capacitor electrode portion for a sufficient distance to place said bottom electrode portion within an angle drawn from a point on said top capacitor electrode portion, said angle ranging from 30° to 70° relative to a perpendicular line taken from one of said electrodes.
Claim 2
Independent Claim
114 words
A method of fabricating an integrated circuit comprising: providing a semiconducting wafer including a semiconducting substrate; forming a bottom capacitor electrode, a ferroelectric layer, and a top capacitor electrode without intervening photo-mask steps; patterning said ferroelectric capacitor circuit to provide an edge having an outer bottom capacitor electrode portion, an outer ferroelectric layer portion, and a top capacitor electrode portion, said bottom capacitor electrode portion extending outwardly beyond said top capacitor electrode portion for a sufficient distance to place said bottom electrode portion within an angle drawn from a point on said top capacitor electrode portion, said angle ranging from 30° to 70° relative to a perpendicular line taken from one of said electrodes.
Claim 3
Dependent Claim
89 words
A method of fabricating an integrated circuit as in claim 1 wherein said step of patterning comprises the steps of: patterning said top capacitor electrode in a first photo mask step using a first photo-mask to provide said outer top capacitor electrode portion; and patterning at least a portion of said ferroelectric layer and said bottom capacitor electrode in a second photo-mask step using a second photo-mask having a larger area than said first photo-mask to provide said outer ferroelectric layer portion and said outer bottom capacitor electrode portion.
Claim 4
Dependent Claim
30 words
A method as in claim 1 wherein said step of patterning includes a step of creating a gradual taper from said top electrode across said ferroelectric layer to said electrode.
Claim 5
Dependent Claim
48 words
A method as in claim 1 wherein said patterning step includes a step of inclining the substrate at said angle relative to an ion-etching beam to provide a uniform taper across said outer bottom capacitor electrode portion, said outer ferroelectric layer portion, and said top capacitor electrode portion.
Claim 6
Dependent Claim
51 words
The method as set forth in claim 1, further including a step of depositing a barrier layer over said bottom capacitor electrode, wherein said barrier layer comprises a material from the group consisting of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, and ruthenium oxide.
Claim 7
Dependent Claim
36 words
The method as set forth in claim 5, further including steps of manufacturing a transistor on said substrate proximal to said ferroelectric capacitor and connecting said transistor with said ferroelectric capacitor to form a memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-13 | 1999-05-15 | 1999-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-13 | 2003-05-15 | 2003-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-13 | 2007-05-15 | 2007-11-14 | $7700.00 | Window Closed / Lapsed |