Patent US3104693A successfully refreshed from Google Patents.
Patent US5451888A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5451888A Expired / Lapsed US ⏱️ 0.0 years remaining

Direct coupled FET logic translator circuit

Assignee: Mitsubishi Electric Corp
•
Filing: 1993-10-19
•
Granted: 1995-09-19
•
Expires: 2013-10-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A semiconductor circuit for converting high and low input signals at first and second voltage levels to high and low output signals at third and fourth voltage levels includes first, second, and third power supply lines receiving driving voltages at first, second, and third voltages, respectively, the third voltage being intermediate the first and second voltages, a first logic circuit connected to and driven by the first and third power supply lines for receiving high and low input signals at first and second voltage levels and producing output signals in response, a second logic circuit connected to and driven by the second and third power supply lines for receiving input signals and producing high and low output signals at third and fourth voltage levels in response, a level converting circuit connected to and driven by the first and second power supply lines, receiving the output signals of the first logic circuit and supplying input signals to the second logic circuit, a switching element and a load element connected in series and to the first and second power supply lines, the junction of the switching and load elements being connected to the second logic circuit, the switching element being connected to and controlled by the first logic circuit, and a clamping circuit connected in parallel with the load element in order to operate at high speed.

Inventors

  • 👤 Masaaki Shimada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 18:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 234 words
A semiconductor circuit for converting high and low input signals at respective first and second voltage levels to high and low output signals at respective third and fourth voltage levels comprising: first, second, and third power supply lines for receiving driving voltages at first, second, and third voltages, respectively, the third voltage being intermediate the first and second voltages; a first logic circuit connected to and driven by the first and third power supply lines for receiving high and low input signals at respective first and second voltage levels and producing output signals in response; a second logic circuit connected to and driven by the second and third power supply lines for receiving input signals and producing high and low output signals at respective third and fourth voltage levels in response; and a level converting circuit connected to and driven by the first and second power supply lines, receiving the output signals of the first logic circuit, and supplying input signals to the second logic circuit and comprising a switching element and a load element connected in series to each other, the series connection of elements being connected to the first and second power supply lines, the junction of said switching and load elements being connected to the second logic circuit, the switching element receiving the output signal of the first logic circuit; and a clamping circuit connected in parallel with said load element.
Claim 2
Dependent Claim 234 words
A semiconductor circuit for converting high and low input signals at respective first and second voltage levels to high and low output signals at respective third and fourth voltage levels comprising: first, second, and third power supply lines for receiving driving voltages at first, second, and third voltages, respectively, the third voltage being intermediate the first and second voltages; a first logic circuit connected to and driven by the first and third power supply lines for receiving high and low input signals at respective first and second voltage levels and producing output signals in response; a second logic circuit connected to and driven by the second and third power supply lines for receiving input signals and producing high and low output signals at respective third and fourth voltage levels in response; and a level converting circuit connected to and driven by the first and second power supply lines, receiving the output signals of the first logic circuit, and supplying input signals to the second logic circuit and comprising a switching element and a load element connected in series to each other, the series connection of elements being connected to the first and second power supply lines, the junction of said switching and load elements being connected to the second logic circuit, the switching element receiving the output signal of the first logic circuit; and a clamping circuit connected in parallel with said load element.
Claim 3
Dependent Claim 20 words
The simiconductor circuit of claim 1, wherein said claiming circuit comprises two Schottky diodes connected in series with each other.
Claim 4
Dependent Claim 58 words
The semiconductor circuit of claim 1, wherein said switching element includes a first transistor having a gate and a second transistor having a gate, said first and second transistors being connected in parallel and said first logic circuit comprises first and second inverters having respective output terminals connected respectively to the gates of said first and second transistors.
Claim 5
Dependent Claim 26 words
The semiconductor circuit of claim 3, wherein said load element comprises a plurality of load transistors having predetermined gate widths connected in parallel with each other.
Claim 6
Dependent Claim 40 words
The semiconductor circuit of claim 3, wherein said load element is a load transistor having a predetermined gate width so that the input signal supplied by said level converting circuit is an ideal voltage when said switching element is on.

References Cited (Backward Citations)

US4743782A Cited
JPS6212211A Cited
US4707622A Cited
JPS6390918A Cited
US4897565A Cited
EP0366294A2 Cited
US5107144A Cited
US5043607A Cited
US5159208A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-09-18 1999-03-20 1999-09-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-09-18 2003-03-20 2003-09-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-09-18 2007-03-20 2007-09-19 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag