US4707622A
Expired / Lapsed
US
⏱️ 0.0 years remaining
GaAs MESFET logic buffers using enhancement and depletion FETs
Assignee: Fujitsu Ltd
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Filing: 1985-12-31
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Granted: 1987-11-17
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Expires: 2005-12-31
Abstract
Abstract A logic circuit includes an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input, and a first depletion type transistor having a gate and a source which are directly connected to a drain of the first enhancement type field effect transistor. A source follower circuit including a second enhancement type field effect transistor having a gate is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor. A second depletion type field effect transistor having a gate and a source which are directly connected to each other has a drain which is connected to a source of the second enhancement type field effect transistor. A first power source is connected to the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor and a second power source is connected to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor. An output is formed at the connecting point of the second enhancement type field effect transistor and the second depletion type field effect type transistor.
Inventors
- 👤 Hisoka Takao
- 👤 Toshiro Sato
- 👤 Seiichi Saito
- 👤 Toshinari Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/0952
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
231 words
A logic circuit, for connection to first and second power sources, comprising: an input; an inverter circuit including: a first enhancement type field effect transistor having a gate connected to the input and having a drain; and a first depletion type field effect transistor having a gate and a source which are directly connected to the drain of said first enhancement type field effect transistor at a connecting point; a source follower circuit including: a second enhancement type field effect transistor having a gate which is connected to the connecting point of said first enhancement type field effect transistor and said first depletion type field effect transistor; and a second depletion type field effect transistor having a gate and a source which are directly connected to each other and having a drain which is connected to the source of said second enhancement type field effect transistor at a connecting point, the drains of said first depletion type field effect transistor and said second enhancement type field effect transistor are connected to the first power source, and the sources of said first enhancement type field effect transistor and said second depletion type field effect transistor are connected to the second power source; and an output, formed at the connecting point of said second enhancement type field effect transistor and said second depletion type field effect transistor which forms said source follower circuit.
Claim 2
Dependent Claim
231 words
A logic circuit, for connection to first and second power sources, comprising: an input; an inverter circuit including: a first enhancement type field effect transistor having a gate connected to the input and having a drain; and a first depletion type field effect transistor having a gate and a source which are directly connected to the drain of said first enhancement type field effect transistor at a connecting point; a source follower circuit including: a second enhancement type field effect transistor having a gate which is connected to the connecting point of said first enhancement type field effect transistor and said first depletion type field effect transistor; and a second depletion type field effect transistor having a gate and a source which are directly connected to each other and having a drain which is connected to the source of said second enhancement type field effect transistor at a connecting point, the drains of said first depletion type field effect transistor and said second enhancement type field effect transistor are connected to the first power source, and the sources of said first enhancement type field effect transistor and said second depletion type field effect transistor are connected to the second power source; and an output, formed at the connecting point of said second enhancement type field effect transistor and said second depletion type field effect transistor which forms said source follower circuit.
Claim 3
Dependent Claim
86 words
A logic circuit according to claim 1, wherein the second power source supplies a voltage to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor, producing, when a predetermined high voltage level is supplied to the input, the following relationship: V.sub.OLN -V.sub.SS ≦V.sub.thE, where V OLN is the output voltage of said inverter circuit, V SS is the second power source voltage, and V thE is the threshold voltage of said second enhancement type field effect transistor.
Claim 4
Dependent Claim
85 words
A logic circuit according to claim 2, wherein said field effect transistors are MES field effect transistors, each having a gate and a source, each of said MES field effect transistors inherently having a Schottky diode coupled between its gate and its source, producing, when the first power source voltage is higher than V SS , the following relationship: V.sub.DD -V.sub.SS <2 V.sub.F, where V DD is the first power source voltage, and V F is the forward voltage of each of said Schottky diodes.
Claim 5
Dependent Claim
19 words
A logic circuit according to claim 1 or 2, wherein said field effect transistors are MIS field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-16 | 1991-05-18 | 1991-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-16 | 1995-05-18 | 1995-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-16 | 1999-05-18 | 1999-11-17 | $7700.00 | Window Closed / Lapsed |