GaAs level-shift logic interface circuit

Claim 2

A solid state monolithic integrated circuit, comprising: a substrate of a material selected from the group consisting of gallium arsenide and indium phosphide; an input node; means for converting the logic levels of digital input signals having a first voltage swing to second digital signals having a second voltage swing, wherein said second voltage swing has a larger magnitude than said first voltage swing, said converting means is integral with said substrate and receives only one digital input signal at a time, and said converting means includes two cascaded single input stages, with each of said stages including a switching metal-semiconductor field effect transistor (MESFET) having a control gate, wherein said control gate of the first of said stages is connected to said input node, and the output of the first of said stages is applied to said gate of said MESFET in the second of said stages to control the flow of current in said MESFET in said second of said stages; and means for amplifying said second digital signals, coupled to said second of said stages.

Claim 3

The circuit of claim 1, further comprising means for inverting said second digital signals prior to amplification of said second digital signals by said amplifying means.

Claim 4

A solid state monolithic integrated circuit, comprising: a substrate of a material selected from the group consisting of gallium arsenide and indium phosphide; means for converting the logic levels of digital input signals having a first voltage swing to second digital signals having a second voltage swing, wherein said second voltage swing has a larger magnitude than said first voltage swing, said converting means is integral with said substrate and receives only one digital input signal at a time, said converting means including: first means for inverting said digital input signal to a first digital inverted signal, first means for shifting the voltage level of said first digital inverted signal to a first digital shifted signal, second means for inverting said first digital shifted signal to a second digital inverted signal, second means for shifting the voltage level of said second digital inverted signal to a second digital shifted signal, third means for inverting said second digital shifted signal to a third digital inverted signal, third means for shifting the voltage level of said third digital inverted signal to a third digital shifted signal, and fourth means for inverting said third digital shifted signal to a fourth digital inverted signal being said second digital signals; and means for amplifying said fourth digital inverted signal to generate an amplified digital signal having a third voltage swing with a magnitude greater than the magnitude of said second voltage swing.

Claim 5

A solid state monolithic integrated circuit, comprising: a substrate of a material selected from the group consisting of gallium arsenide and indium phosphide; means for converting the logic levels of digital input signals having a first voltage swing to second digital signals having a second voltage swing, wherein said second voltage swing has a larger magnitude than said first voltage swing, said converting means is integral with said substrate and receives only one digital input signal at a time, said converting means including: first means for inverting said digital input signal to a first digital inverted signal, first means for shifting the voltage level of said first digital inverted signal to a first digital shifted signal, second means for inverting said first digital shifted signal to a second digital inverted signal, second means for shifting the voltage level of said second digital inverted signal to a second digital shifted signal, third means for inverting said second digital shifted signal to a third digital inverted signal, third means for shifting the voltage level of said third digital inverted signal to a third digital shifted signal, and fourth means for inverting said third digital shifted signal to a fourth digital inverted signal being said second digital signals; and means for amplifying said fourth digital inverted signal to generate an amplified digital signal having a third voltage swing with a magnitude greater than the magnitude of said second voltage swing.

Claim 6

The circuit of claim 3 wherein said circuit is connected to first and second voltage supplies and a voltage reference point, and wherein: said first inverting means includes first, second and third depletion mode metal semiconductor field effect transistors (MESFETS) each having a drain, a gate and a source, wherein the drain of said first MESFET is connected to said first voltage supply, and the source of said first MESFET is connected to the gate of said first MESFET and to the drain of said second MESFET, the gate of said second MESFET receives said digital input signals, the source of said second MESFET is connected to the drain of said third MESFET, and the source of said third MESFET is connected to the gate of said third MESFET and to said second voltage supply; said first voltage level shifting means includes first and second Schottky diodes connected in series; said second inverter means includes fourth and fifth depletion mode MESFETS each having a drain, a gate and a source, wherein the drain of said fourth MESFET is connected to said first voltage supply, the source of said fourth MESFET is connected to the gate of said fourth MESFET and to the drain of said fifth MESFET, the source of said fifth MESFET is connected to said voltage reference point, and the gate of said fifth MESFET is connected to the output of said first voltage level shifting means; said second voltage level shifting means includes third, fourth and fifth Schottky diodes connected in series; said third inverter means includes sixth and seventh depletion mode MESFETS each having a drain, a gate and a source, wherein the drain of said sixth MESFET is connected to said first voltage supply, the source of said sixth MESFET is connected to the gate of said sixth MESFET and to the drain of said seventh MESFET, the gate of said seventh MESFET is connected to the output of said second voltage level shifting means and the source of said seventh MESFET is connected to said voltage reference point; said third voltage level shifting means includes sixth, seventh and eighth Schottky diodes connected in series; said fourth inverter means includes eighth and ninth depletion mode MESFETS and said amplifier means also includes said eighth and ninth depletion mode MESFETS each having a drain, a gate and a source, wherein the drain of said eighth MESFET is connected to said first voltage supply, the source of said eighth MESFET is connected to the gate of said eighth MESFET and to the drain of said ninth MESFET, the gate of said ninth MESFET is connected to the output of said third voltage level shifting means and the source of said ninth MESFET is connected to said voltage reference point.

Claim 7

The circuit of claim 3 wherein the logic levels of said digital input signals are derived from an emitter coupled logic (ECL) integrated circuit; and said amplifying means is used to drive an analog electrical device.