US4488064A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with a common power supply for silicon and gallium arsenide circuit portions
Assignee: International Standard Electric Corp
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Filing: 1982-08-03
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Granted: 1984-12-11
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Expires: 2002-08-03
Abstract
Abstract A gallium arsenide logic circuit which forms part of a silicon/gallium arsenide logic interface, is provided with a negative supply voltage from a silicon logic gate whose output is held in its LOW condition. This obviates the need to provide separate power supplies to the two different semiconductor types.
Inventors
- 👤 Ian A. W. Vance
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/017545; H03K19/02; H03K19/08; H03K19/094; H03K19/0952
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
136 words
A semi-conductor circuit arrangement powered from an electric power supply which provides a predetermined voltage differential, comprising: a first circuit portion powered from the power supply and including a silicon integrated circuit provided with at least one logic gate having a control input and an output; a second circuit portion including a gallium arsenide integrated circuit having a reference voltage input connected to the power supply and a power voltage input; means for applying such an electric potential to said control input as to maintain said logic gate, in use, in its low state; and means for coupling said logic gate output to said power supply voltage input, so that, in use, the power supply voltage for the gallium arsenide integrated circuit is derived from the output voltage of said logic gate in its low state.
Claim 2
Dependent Claim
136 words
A semi-conductor circuit arrangement powered from an electric power supply which provides a predetermined voltage differential, comprising: a first circuit portion powered from the power supply and including a silicon integrated circuit provided with at least one logic gate having a control input and an output; a second circuit portion including a gallium arsenide integrated circuit having a reference voltage input connected to the power supply and a power voltage input; means for applying such an electric potential to said control input as to maintain said logic gate, in use, in its low state; and means for coupling said logic gate output to said power supply voltage input, so that, in use, the power supply voltage for the gallium arsenide integrated circuit is derived from the output voltage of said logic gate in its low state.
Claim 3
Dependent Claim
16 words
A circuit arrangement as claimed in claim 1, wherein said coupling means comprises a voltage follower.
Claim 4
Dependent Claim
23 words
A circuit arrangement as claimed in either of claims 1 or 2, wherein said logic gate is an emitter coupled logic (ECL) gate.
Claim 5
Dependent Claim
20 words
A circuit arrangement as claimed in either of claims 1 or 2, wherein said second circuit portion is a multiplexer.
Claim 6
Dependent Claim
20 words
A circuit arrangement as claimed in either of claims 1 or 2, wherein said second circuit portion is a demultiplexer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |