US4410815A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gallium arsenide to emitter coupled logic level converter
Assignee: Samsung Electronics Co Ltd
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Filing: 1981-09-24
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Granted: 1983-10-18
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Expires: 2001-09-24
Abstract
Abstract A high speed gallium arsenide (GaAs) integrated circuit is provided which converts GaAs input or source signals to voltage levels for directly driving emitter coupled logic (ECL) circuits. The high speed GaAs level converter comprises a level shifting network at the input, two stages of differential amplification and a novel source follower output stage.
Inventors
- 👤 Stephen A. Ransom
- 👤 Tedd K. Stickel
- 👤 Joseph B. Tomei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09432; H03K19/09436; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/018542
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
245 words
A gallium arsenide (GaAs) level converter for employing gallium arsenide logic source input signals to drive emitter coupled logic (ECL) circuitry, comprising: a non-inverting gallium arsenide logic source input, an inverting gallium arsenide logic source input, a plurality of series connected gallium arsenide level shifting diodes connected in each said gallium arsenide logic source input, a voltage source, a first gallium arsenide differential amplifier connected to said voltage source, said first gallium arsenide differential amplifier having a non-inverting input transistor whose gate is coupled to said non-inverting gallium arsenide logic source input and having an inverting input transistor whose gate is coupled to the inverting logic source input, a resistive pull-up load connected intermediate said voltage source and the drain of said inverting input transistor, a low reference voltage, a resistive common source impedance connected between the source of said input transistors and said low reference voltage, an output line connected to the drain of said inverting input transistor, a termination voltage, an output load branch having a series connected gallium arsenide transistor, a gallium arsenide level shifting diode and a precision termination resistor connected between said voltage source and said termination voltage, said output key being connected to the gate of said output load branch transistor, and a converter output line connected intermediate said gallium arsenide diode and said precision termination resistor, whereby said converter output line is provided with a full range of output voltage swings adapted to drive emitter coupled logic loads.
Claim 2
Dependent Claim
245 words
A gallium arsenide (GaAs) level converter for employing gallium arsenide logic source input signals to drive emitter coupled logic (ECL) circuitry, comprising: a non-inverting gallium arsenide logic source input, an inverting gallium arsenide logic source input, a plurality of series connected gallium arsenide level shifting diodes connected in each said gallium arsenide logic source input, a voltage source, a first gallium arsenide differential amplifier connected to said voltage source, said first gallium arsenide differential amplifier having a non-inverting input transistor whose gate is coupled to said non-inverting gallium arsenide logic source input and having an inverting input transistor whose gate is coupled to the inverting logic source input, a resistive pull-up load connected intermediate said voltage source and the drain of said inverting input transistor, a low reference voltage, a resistive common source impedance connected between the source of said input transistors and said low reference voltage, an output line connected to the drain of said inverting input transistor, a termination voltage, an output load branch having a series connected gallium arsenide transistor, a gallium arsenide level shifting diode and a precision termination resistor connected between said voltage source and said termination voltage, said output key being connected to the gate of said output load branch transistor, and a converter output line connected intermediate said gallium arsenide diode and said precision termination resistor, whereby said converter output line is provided with a full range of output voltage swings adapted to drive emitter coupled logic loads.
Claim 3
Dependent Claim
26 words
A level converter as set forth in claim 1 wherein said precision termination resistor is provided as an external component connected to said gallium arsenide converter.
Claim 4
Dependent Claim
28 words
A level converter as set forth in claim 2 wherein said converter output line is connected to a transmission line having a characteristic impedance of approximately 50 ohms.
Claim 5
Dependent Claim
29 words
A level converter as set forth in claim 1 wherein said resistive pull-up load comprises a gallium arsenide current source transistor for controlling current in said output load branch.
Claim 6
Dependent Claim
56 words
A level converter as set forth in claim 4 which further includes a second gallium arsenide differential amplifier having a pair of input transistors and an output line connected to the gate of said current source load transistor, each of said pair of input transistors having their gates coupled to one of said logic input sources.
Claim 7
Dependent Claim
31 words
A level converter as set forth in claim 5 wherein said second gallium arsenide differential amplifier further comprises a gallium arsenide current source load transistor and a current source pull-down transistor.
Claim 8
Dependent Claim
21 words
A level converter as set forth in claim 1 wherein said resistive common source impedance comprises a controlled current source transistor.
Claim 9
Dependent Claim
28 words
A level converter as set forth in claim 7 wherein said inverting gallium arsenide logic input source is coupled to the gate of said controlled current source transistor.
Claim 10
Dependent Claim
48 words
A level converter as set forth in claim 8 wherein a level shifting network comprising said plurality of level shifting diodes and a gallium arsenide current source pull-down transistor is coupled intermediate said inverting gallium arsenide logic input source and the gate of said controlled current source transistor.
Claim 11
Dependent Claim
33 words
A level converter as set forth in claim 9 wherein said level shifting network is also coupled intermediate said inverting gallium arsenide logic input source and the gate of said inverting input transistor.
Claim 12
Dependent Claim
30 words
A level converter as set forth in claim 8 which further includes a gate resistor coupled intermediate said level shifting network and the gate of said controlled current source transistor.
Claim 13
Dependent Claim
52 words
A level converter as set forth in claim 8 wherein a level shifting network comprising said plurality of level shifting diodes and a gallium arsenide current source pull-down transistor are coupled intermediate said non-inverting gallium arsenide logic source input and the gate of said non-inverting input transistor of said first differential amplifier.
References Cited (Backward Citations)
US3716722A
Cited
US4237388A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-17 | 1987-04-18 | 1987-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-17 | 1991-04-18 | 1991-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-17 | 1995-04-18 | 1995-10-18 | $7700.00 | Window Closed / Lapsed |