US4237388A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Inverter circuit
Assignee: NEC Corp
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Filing: 1978-06-14
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Granted: 1980-12-02
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Expires: 1998-06-14
Abstract
Abstract An inverter circuit operating at a high speed and with low power consumption is disclosed, which comprises a first bipolar transistor having a collector coupled to the output of the circuit, a second bipolar transistor having a collector coupled to the base of the first transistor and means responsive to at least one input signal to produce a first signal for driving the first transistor and a second signal complementary to the first signal for driving the second transistor substantially at the same time.
Inventors
- 👤 Jyoji Nokubo
- 👤 Hiroshi Mayumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
260 words
An inverter circuit comprising an output terminal, a first bipolar transistor having a collector coupled to said output terminal, a second bipolar transistor having a collector coupled to the base of said first transistor, a current mode logic circuit including third and fourth bipolar transistors having emitters jointly connected to a common junction point and a power supply, first means for controlling said first transistor, said first means including a fifth bipolar transistor having a base coupled to the collector of said third transistor and an emitter coupled to the base of said first transistor, a second means for controlling said second transistor, said second means including a sixth bipolar transistor having a base coupled to the collector of said fourth transistor and an emitter coupled to the base of said second transistor, first clamp means including a seventh bipolar transistor having a collector coupled to the emitter of said fifth transistor and an emitter coupled to the collector of said first transistor, a first resistor coupled between the collector and the base of said seventh transistor and a second resistor coupled between the base of said seventh transistor and the base of said first transistor, and second clamp means including an eighth bipolar transistor having a collector coupled to the emitter of said sixth transistor and an emitter coupled to the collector of said second transistor, a third resistor coupled between the collector and the base of said eighth transistor and a fourth resistor coupled between the base of said eighth transistor and the base of said second transistor.
Claim 2
Dependent Claim
260 words
An inverter circuit comprising an output terminal, a first bipolar transistor having a collector coupled to said output terminal, a second bipolar transistor having a collector coupled to the base of said first transistor, a current mode logic circuit including third and fourth bipolar transistors having emitters jointly connected to a common junction point and a power supply, first means for controlling said first transistor, said first means including a fifth bipolar transistor having a base coupled to the collector of said third transistor and an emitter coupled to the base of said first transistor, a second means for controlling said second transistor, said second means including a sixth bipolar transistor having a base coupled to the collector of said fourth transistor and an emitter coupled to the base of said second transistor, first clamp means including a seventh bipolar transistor having a collector coupled to the emitter of said fifth transistor and an emitter coupled to the collector of said first transistor, a first resistor coupled between the collector and the base of said seventh transistor and a second resistor coupled between the base of said seventh transistor and the base of said first transistor, and second clamp means including an eighth bipolar transistor having a collector coupled to the emitter of said sixth transistor and an emitter coupled to the collector of said second transistor, a third resistor coupled between the collector and the base of said eighth transistor and a fourth resistor coupled between the base of said eighth transistor and the base of said second transistor.
Claim 3
Dependent Claim
367 words
An inverter circuit comprising an output terminal, a first potential source, a second potential source, a first bipolar transistor having a collector coupled to said output terminal and an emitter coupled to said second potential source, a second bipolar transistor having a collector coupled to the base of said first transistor and an emitter coupled to said second potential source, a current mode logic circuit including a constant current source, a first load means, a second load means, a third bipolar transistor having a collector coupled to said first potential source through said first load means, and a fourth bipolar transistor having a collector coupled to said first potential source through said second load means, emitters of said third and fourth transistors being jointly coupled to said second potential source through said constant current source, first control means including a first diode and a fifth bipolar transistor having a collector coupled to said first potential source, a base coupled to the collector of said third transistor and an emitter coupled to the base of said first transistor through said first diode and to said second potential source and second control means including a second diode and a sixth bipolar transistor having a collector coupled to said first potential source, a base coupled to the collector of said fourth transistor and an emitter coupled to the base of said second transistor through said second diode and to said second potential source, first clamp means including a seventh bipolar transistor having a collector coupled to the emitter of said fifth transistor and an emitter coupled to the collector of said first transistor, a first resistor coupled between the collector and the base of said seventh transistor and a second resistor coupled between the base of said seventh transistor and the base of said first transistor, and second clamp means including an eighth bipolar transistor having a collector coupled to the emitter of said sixth transistor and an emitter coupled to the collector of said second transistor, a third resistor coupled between the collector and the base of said eighth transistor and a fourth resistor coupled between the base of said eighth transistor and the base of said second transistor.
Claim 4
Dependent Claim
367 words
An inverter circuit comprising an output terminal, a first potential source, a second potential source, a first bipolar transistor having a collector coupled to said output terminal and an emitter coupled to said second potential source, a second bipolar transistor having a collector coupled to the base of said first transistor and an emitter coupled to said second potential source, a current mode logic circuit including a constant current source, a first load means, a second load means, a third bipolar transistor having a collector coupled to said first potential source through said first load means, and a fourth bipolar transistor having a collector coupled to said first potential source through said second load means, emitters of said third and fourth transistors being jointly coupled to said second potential source through said constant current source, first control means including a first diode and a fifth bipolar transistor having a collector coupled to said first potential source, a base coupled to the collector of said third transistor and an emitter coupled to the base of said first transistor through said first diode and to said second potential source and second control means including a second diode and a sixth bipolar transistor having a collector coupled to said first potential source, a base coupled to the collector of said fourth transistor and an emitter coupled to the base of said second transistor through said second diode and to said second potential source, first clamp means including a seventh bipolar transistor having a collector coupled to the emitter of said fifth transistor and an emitter coupled to the collector of said first transistor, a first resistor coupled between the collector and the base of said seventh transistor and a second resistor coupled between the base of said seventh transistor and the base of said first transistor, and second clamp means including an eighth bipolar transistor having a collector coupled to the emitter of said sixth transistor and an emitter coupled to the collector of said second transistor, a third resistor coupled between the collector and the base of said eighth transistor and a fourth resistor coupled between the base of said eighth transistor and the base of said second transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-02 | 1984-06-02 | 1984-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-02 | 1988-06-02 | 1988-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-02 | 1992-06-02 | 1992-12-02 | $7700.00 | Window Closed / Lapsed |