Interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit

Claim 2

An interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit, said interface circuit comprising: input buffer means for receiving an input signal from the compound semiconductor logic circuit and for outputting a buffered input signal; an output transistor having a gate connectable to receive said drive signal, a first terminal connectable to receive a first power supply voltage, and a second terminal, an output terminal connected to said second terminal of said output transistor and said bipolar transistor circuit; and output level adjustment means, comprising a first Schottky barrier transistor having a gate, a first terminal connected to the gate of said first Schottky barrier transistor and the gate of said output transistor, and a second terminal, for generating a constant voltage and applying the constant voltage to the second terminal of said first Schottky barrier transistor and wherein said output level adjustment means further comprises a first level shift element having a first terminal coupled to said first power supply voltage and a second terminal coupled to the second terminal of said first Schottky barrier transistor.

Claim 3

An interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit, said interface circuit comprising: input buffer means for receiving an input signal from the compound semiconductor logic circuit and for outputting a buffered input signal; output driving means, operatively coupled to said input buffer means, for generating a drive signal from said buffered input signal; an output transistor having a gate connectable to receive said drive signal, a first terminal connectable to receive a first power supply voltage, and a second terminal; an output terminal connected to said second terminal of said output transistor and said bipolar transistor circuit; and output level adjustment means, comprising a first Schottky barrier transistor having a gate, a first terminal connected to the gate of said first Schottky barrier transistor and the gate of said output transistor, and a second terminal, for generating a constant voltage and applying the constant voltage to the second terminal of said first Schottky barrier transistor, and wherein said output level adjustment means further comprises: a first level shift element having a first terminal connectable to receive said first power supply voltage, and a second terminal; and a second Schottky barrier transistor having a gate connectable to receive a second power supply voltage lower than said first power supply voltage, a first terminal connected to the second terminal of said first level shift element and the second terminal of said first Schottky barrier transistor, and a second terminal connectable to receive said second power supply voltage.

Claim 4

An interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit, said interface circuit comprising: input buffer means for receiving an input signal from the compound semiconductor logic circuit and for outputting a buffered input signal; output driving means, operatively coupled to said input buffer means, for generating a drive signal from said buffered input signal; an output transistor having a gate connectable to receive said drive signal, a first terminal connectable to receive a first power supply voltage, and a second terminal; an output terminal connected to said second terminal of said output transistor and said bipolar transistor circuit; and output level adjustment means, comprising a first Schottky barrier transistor having a gate, a first terminal connected to the gate of said first Schottky barrier transistor and the gate of said output transistor, and a second terminal, for generating a constant voltage and applying the constant voltage to the second terminal of said first Schottky barrier transistor, and wherein said output level adjustment means further comprises: a first level shift element having a first terminal connectable to receive said first power supply voltage, and a second terminal; and a second Schottky barrier transistor having a gate connectable to receive a second power supply voltage lower than said first power supply voltage, a first terminal connected to the second terminal of said first level shift element and the second terminal of said first Schottky barrier transistor, and a second terminal connectable to receive said second power supply voltage.

Claim 5

An interface circuit as claimed in claim 2, wherein said output level adjustment means further comprises protection means for preventing a reverse current from passing through said second and first Schottky barrier transistors so that said first Schottky barrier transistor is prevented from being damaged due to said reverse current.

Claim 6

An interface circuit as claimed in claim 2, wherein: said first Schottky barrier transistor is an enhancement type field effect transistor; and said second Schottky barrier transistor is a depletion type field effect transistor.

Claim 7

An interface circuit as claimed in claim 2, wherein said first level shift element comprises a level shift diode.

Claim 8

An interface circuit as claimed in claim 2, wherein said output level adjustment means further comprises a capacitor having a first terminal connected to the gate of said output transistor, and a second terminal connectable to receive said second power supply voltage.

Claim 9

An interface circuit as claimed in claim 2, wherein said output driving mean further comprises: a third Schottky barrier transistor having a first terminal connectable to receive said first power supply voltage, a second terminal and a gate connected to said second terminal of said third Schottky barrier transistor and the gate of said output transistor; a fourth Schottky barrier transistor having a first terminal connected to the gate of said output transistor, a gate connected to the first terminal of said fourth Schottky barrier transistor, and a second terminal; and a fifth Schottky barrier transistor having a first terminal connected to the second terminal of said fourth Schottky barrier transistor, a second terminal connectable to receive said second power supply voltage, and a gate connectable to receive said buffered input signal.

Claim 10

An interface circuit as claimed in claim 3, wherein said protection means comprises a first diode having an anode, connected to the second terminal of said first Schottky barrier transistor, and a cathode, connected to the first terminal of said second Schottky barrier transistor.

Claim 11

An interface circuit as claimed in claim 8, wherein said protection means further comprises a second diode, having an anode connected to the second terminal of said first level shift element, and a cathode, connected to the first terminal of said second Schottky barrier transistor.

Claim 12

An interface circuit as claimed in claim 9, wherein said output level adjustment means comprises a capacitor having a first terminal connected to the gate of said output transistor, and a second terminal connectable to receive said second power supply voltage.

Claim 13

An interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit, said interface circuit comprising: input buffer means for receiving an input signal from the compound semiconductor logic circuit and for outputting a buffered input signal; output driving means, operatively coupled to said input buffer means, for generating a drive signal from said buffered input signal; an output transistor having a gate connectable to receive said drive signal, a first terminal connectable to receive a first power supply voltage, and a second terminal; an output terminal connected to said second terminal of said output transistor and said bipolar transistor circuit; and output level adjustment means, comprising a first Schottky barrier transistor having a gate, a first terminal connected to the gate of said first Schottky barrier transistor and the gate of said output transistor, and a second terminal, for generating a constant voltage and applying the constant voltage to the second terminal of said first Schottky barrier transistor wherein said output level adjustment means further comprises means, connectable to receive said first power supply voltage and a second power supply voltage lower than said first power supply voltage, for generating said constant voltage from said first power supply voltage and said second power supply voltage and wherein said output level adjustment means further comprises a first level shift element having a first terminal coupled to said first power supply voltage and a second terminal connected to the second terminal of said first Schottky barrier transistor.

Claim 14

An interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit, said interface circuit comprising: input buffer means for receiving an input signal from the compound semiconductor logic circuit and for outputting a buffered input signal; output driving means, operatively coupled to said input buffer means, for generating a drive signal from said buffered input signal; an output transistor having a gate connectable to receive said drive signal, a first terminal connectable to receive a first power supply voltage, and a second terminal; an output terminal connected to said second terminal of said output transistor and said bipolar transistor circuit; and output level adjustment means, comprising a first Schottky barrier transistor having a gate, a first terminal connected to the gate of said first Schottky barrier transistor and the gate of said output transistor, and a second terminal, for generating a constant voltage and applying the constant voltage to the second terminal of said first Schottky barrier transistor wherein said output level adjustment means further comprises means, connectable to receive said first power supply voltage and a second power supply voltage lower than said first power supply voltage, for generating said constant voltage from said first power supply voltage and said second power supply voltage and wherein said output level adjustment means further comprises a first level shift element having a first terminal coupled to said first power supply voltage and a second terminal connected to the second terminal of said first Schottky barrier transistor.

Claim 15

An interface circuit as claimed in claim 11, wherein said input buffer means is connected so that said input buffer means receives said first power supply voltage and a third power supply voltage lower than said first power supply voltage.

Claim 16

An interface circuit as claimed in claim 11, wherein said input buffer means is connected so that said input buffer means receives said first power supply voltage and said second power supply voltage.

Claim 17

An interface circuit as claimed in claim 11, further comprising level shifting means, connectable to receive said first power supply voltage and said second power supply voltage, for receiving said buffered input signal and for generating a level-shifted signal from said buffered input signal, said level-shifted signal being applied to said output driving means.

Claim 18

An interface circuit as claimed in claim 14, wherein said level shifting means comprises: a second Schottky barrier transistor having a first terminal connected to receive said first power supply voltage, a second terminal, and a gate connectable to receive said buffered input signal; a level shift diode having an anode connected to the second terminal of said second Schottky barrier transistor, and a cathode connected to said output driving means; and a fourth Schottky barrier transistor having a first terminal connected to the cathode of said level shift diode, a second terminal connectable to receive said second power supply voltage, and a gate connectable to receive said second power supply voltage.

Claim 19

An interface circuit as claimed in claim 13, wherein said input buffer means comprises: a second Schottky barrier transistor having a first terminal connectable to receive said first power supply voltage, a gate and a second terminal connected to the gate of said second Schottky barrier transistor; a third Schottky barrier transistor having a first terminal connected to the second terminal of said second Schottky barrier transistor, a second terminal connectable to receive said second power supply voltage, and a gate correctable to receive said input signal; a fourth Schottky barrier transistor having a gate connected to the second terminal of said second Schottky barrier transistor, a first terminal connectable to receive said first power supply voltage, and a second terminal connected to said output driving means; and a fifth Schottky barrier transistor having a first terminal connected to the second terminal of said fourth Schottky barrier, a second terminal connectable to receive said second power supply voltage, and a gate connectable to receive said second power supply voltage.

Claim 20

An interface circuit as claimed in claim 1, further comprising super buffer means, connected between said input buffer means and the gate of said output transistor, for driving said output transistor in response to said buffered input signal together with said output driving means.

Claim 21

An interface circuit as claimed in claim 1, further comprising protection means for preventing a reverse current from passing through said output transistor.

Claim 22

An interface circuit as claimed in claim 1, wherein said output transistor is a Schottky barrier field effect transistor.

Claim 23

An interface circuit as claimed in claim 1, wherein said output terminal is connected to an emitter coupled logic circuit.