FET gate current limiter circuits

Claim 2

A logic circuit comprising: input circuit means including at least one input field effect transistor (FET) having a gate for receiving an input signal and having an output terminal coupled to an intermediate node, and first means for biasing said input FET so that in response to the input signal received by said input FET the voltage at said intermediate node nominally varies in response to that of the input signal, said first biasing means providing relatively constant bias current for said input FET; output circuit means including an output FET and second means for biasing said output FET to a high conduction or low conduction state selectively in accordance with the level of voltage applied to a gate of said output FET to produce an output signal having a nominal voltage swing, said voltage applied to said gate of said output FET tending to forward bias said output FET; and limiter means coupled between said gate of said output FET and said intermediate node for limiting the forward biasing of said output FET in response to the input signal to maintain the output voltage swing at the nominal value thereof.

Claim 3

A logic circuit as recited in claim 1, wherein: said limiter means is effective to limit the current to said gate of said output FET so that the voltage at said intermediate node varies in response to that of the input signal.

Claim 4

A logic circuit as recited in claim 1, wherein: said output FET has a parasitic gate-to-source diode; and said limiter means includes a FET having a drain coupled to said intermediate node and an interconnected gate and source coupled to said gate of said output FET, said limiter means being effective to limit the forward biasing of said diode.

Claim 5

A logic circuit as recited in claim 1, wherein: voltage level shift means are connected between said intermediate node and said limiter means for applying to said limiter means a voltage that is shifted from that applied to said intermediate node; and said limiter means is effective in response to the shifted voltage from said voltage level shift means to limit the current to said gate of said output FET to prevent said voltage level shift means and said output FET from becoming increasingly forward biased.

Claim 6

A logic current as recited in claim 1, wherein: voltage level shift means are connected between said intermediate node and said limiter means for applying to said limiter means a voltage that is shifted from that applied to said intermediate node, said voltage level shift means having a voltage drop characteristic that varies in response to the operating temperature of said logic circuit so that at various operating temperatures said voltage level shift means and said output FET tend to become increasingly forward biased; and said limiter means is effective in response to the shifted voltage from said voltage level shift means that tends to increasingly forward bias said output FET to limit the current to said gate of said output FET to prevent said voltage level shift means and said output FET from becoming increasingly forward biased.

Claim 7

A logic circuit for operation under a relatively wide range of operating conditions, comprising: input circuit means including at least one input FET responsive to an input signal for producing an intermediate signal in response to the input signal; means coupled to the input circuit for shifting the voltage level of the intermediate signal by a given amount, said voltage level shift means being responsive to variations in said operating temperature to vary the amount of said voltage level shift; output circuit means including an output FET coupled to said voltage level shift means for response to the level shifted intermediate signal, said output FET having at least one parasitic diode from the gate thereof, said output circuit means also including first means for biasing said output FET to opposite conduction states in response to the level shifted intermediate signal, said first biasing means being variable under operating conditions and tending to heavily forward bias said parasitic diode and said voltage level shift means; second means connected to said output FET and said shifting means for providing relatively constant bias current for said shifting means; and a limiter FET having a drain connected to said voltage level shift means and to said second means and having a gate connected to both its source and to said output FET, said limiter FET being effective when the operating temperature and said first biasing means vary to limit the current to said output FET and limit the forward biasing of said voltage level shift means and said parasitic diode of said output FET.

Claim 8

A logic circuit for operation under a relatively wide range of operating conditions, comprising: input circuit means including at least one input FET responsive to an input signal for producing an intermediate signal in response to the input signal; means coupled to the input circuit for shifting the voltage level of the intermediate signal by a given amount, said voltage level shift means being responsive to variations in said operating temperature to vary the amount of said voltage level shift; output circuit means including an output FET coupled to said voltage level shift means for response to the level shifted intermediate signal, said output FET having at least one parasitic diode from the gate thereof, said output circuit means also including first means for biasing said output FET to opposite conduction states in response to the level shifted intermediate signal, said first biasing means being variable under operating conditions and tending to heavily forward bias said parasitic diode and said voltage level shift means; second means connected to said output FET and said shifting means for providing relatively constant bias current for said shifting means; and a limiter FET having a drain connected to said voltage level shift means and to said second means and having a gate connected to both its source and to said output FET, said limiter FET being effective when the operating temperature and said first biasing means vary to limit the current to said output FET and limit the forward biasing of said voltage level shift means and said parasitic diode of said output FET.

Claim 9

A logic circuit as recited in claim 6, wherein: said voltage level shift means includes a level shift diode, said diode being effective to level shift the voltage of the intermediate signal by a reduced amount as the operating temperature increases so that the voltage level applied to said limiter FET is increased at increased temperature; and said limiter FET being responsive to the increased voltage level of the intermediate signal for limiting the voltage applied to said gate of said output FET to limit the forward biasing of said level shift diode and said parasitic diode of said output FET when said voltage of said intermediate signal increases at increased temperature.

Claim 10

A field effect transistor (FET) diode FET logic integrated circuit for operation under a relatively wide range of operating conditions comprising: a semiconductor; a first FET on said semiconductor and having a gate providing a logic input to the integrated circuit, a source connected to an intermediate logic output and a drain to be coupled to a voltage supply; first means on said semiconductor for biasing said first FET so that in response to an input signal received by said logic input of said first FET the voltage of an intermediate signal at said intermediate logic output nominally varies in response to that of the input signal; at least one Schottky barrier voltage level shift diode on said semiconductor connected to said intermediate logic output for voltage-level-shifting said intermediate signal, said voltage level shift diode being responsive to variations in said operating temperature to vary the amount of said voltage level shift, said shift diode tending to be increasingly forward biased as the operating temperature increases; said first means including a second FET connected to said voltage level shift diode and having a gate thereof connected to a source thereof to provide zero voltage across said gate and said source of said second FET, said second FET providing relatively constant bias circuit for said voltage level shift diode; a third FET on said semiconductor, the drain of said third FET providing a final logic output for said integrated circuit, the gate of said third FET being responsive to the voltage-shifted intermediate signal from said diode, said third FET having a parasitic gate-to-source diode and a parasitic gate-to-drain diode that tend to be increasingly forward biased in response to said intermediate signal; second means for biasing said third FET to a high conduction or a low conduction state selectively in accordance with the level of voltage of the voltage-level-shifted intermediate signal appleid to said gate of said third FET to produce an output signal having a nominal voltage swing, said second biasing means being variable in response to operating conditions to tend to increase the forward bias of said shift diode and said parasitic diodes; and a fourth FET on said semiconductor having an interconnected gate and source connected to said gate of said third FET and a drain connected to said intermediate logic output through said Schottky barrier diode, said fourth FET being effective to limit the current to said gate of said third FET and limit the forward biasing of said shift diode and said parasitic diodes to minimize the variation of output voltage swing from its nominal value and reduce the power dissipated by said circuit.

Claim 11

A field effect transistor (FET) diode FET logic integrated circuit for operation under a relatively wide range of operating conditions comprising: a semiconductor; a first FET on said semiconductor and having a gate providing a logic input to the integrated circuit, a source connected to an intermediate logic output and a drain to be coupled to a voltage supply; first means on said semiconductor for biasing said first FET so that in response to an input signal received by said logic input of said first FET the voltage of an intermediate signal at said intermediate logic output nominally varies in response to that of the input signal; at least one Schottky barrier voltage level shift diode on said semiconductor connected to said intermediate logic output for voltage-level-shifting said intermediate signal, said voltage level shift diode being responsive to variations in said operating temperature to vary the amount of said voltage level shift, said shift diode tending to be increasingly forward biased as the operating temperature increases; said first means including a second FET connected to said voltage level shift diode and having a gate thereof connected to a source thereof to provide zero voltage across said gate and said source of said second FET, said second FET providing relatively constant bias circuit for said voltage level shift diode; a third FET on said semiconductor, the drain of said third FET providing a final logic output for said integrated circuit, the gate of said third FET being responsive to the voltage-shifted intermediate signal from said diode, said third FET having a parasitic gate-to-source diode and a parasitic gate-to-drain diode that tend to be increasingly forward biased in response to said intermediate signal; second means for biasing said third FET to a high conduction or a low conduction state selectively in accordance with the level of voltage of the voltage-level-shifted intermediate signal appleid to said gate of said third FET to produce an output signal having a nominal voltage swing, said second biasing means being variable in response to operating conditions to tend to increase the forward bias of said shift diode and said parasitic diodes; and a fourth FET on said semiconductor having an interconnected gate and source connected to said gate of said third FET and a drain connected to said intermediate logic output through said Schottky barrier diode, said fourth FET being effective to limit the current to said gate of said third FET and limit the forward biasing of said shift diode and said parasitic diodes to minimize the variation of output voltage swing from its nominal value and reduce the power dissipated by said circuit.