Schottky diode field effect transistor logic circuit

Claim 2

A logic circuit having a logic input (50, 72, 136), a logic output (66, 100, 138), a voltage reference point (ground) and being adapted to connect to a first voltage supply (V D D), characterized by: a) a solid substrate; b) a first Schottky diode integral (56, 74, 128) with said substrate and having a first anode and a first cathode, wherein said first anode is directly electrically connected to said logic input (50, 72, 136), said first cathode is comprised of metal and said first cathode is electrically connected to a first node (54, 82); c) a second Schottky diode (58) integral with said substrate and having a second anode and a second cathode, wherein said second cathode is comprised of metal and is directly electrically connected to said logic input, and wherein said second anode is electrically connected to said first node (54, 82); d) current source means (60, 80, 132) electrically connected to said first node; e) a first transistor integral (62, 84, 126) with said substrate and having a first source region, a first drain region and a first control region, wherein said first control region is electrically connected to said first node (54, 82), said first source region is electrically connected to said reference point ground, and said first drain region is electrically connected to said logic output (66, 100, 138); and f) an electrical load means (64, 98, 134) integral with said substrate, wherein said electrical load means is electrically connected to and between said first drain region and said first voltage supply (V D D).

Claim 3

The circuit of claim 1, characterized by:a third Schottky diode (68, 76) having a third anode and a third cathode. wherein said third anode is directly electrically connected to said first cathode and said third cathode is electrically connected to said first node (54, 82) (Fig. 3, 4).

Claim 4

The circuit of claim 1, characterized by: h) a third Schottky diode (114) integral with said substrate and having a third cathode and a third anode. wherein said third cathode is comprised of metal, and wherein said third anode is directly electrically connected to said logic output (66 or 116) and said third cathode is directly electrically connected to a second node (120); i) a fourth Schottky diode (118) integral with said substrate and having a fourth anode and a fourth cathode, wherein said fourth cathode is comprised of metal, and wherein said fourth anode is directly electrically connected to said second node (120) and said fourth cathode is directly electrically connected to said logic output (66 or 116) (Fig. 5).

Claim 5

4 . The circuit of claim 1 or 3, characterized by: j) a first circuit branch between said logic output and a second node (120), said first circuit branch including at least a third Schottky diode (114), said third Schottky diode being adapted to pass substantial current only from said logic- output (116 or 66) to said second node (120); and k) a second circuit branch being said second node and said logic output including at least a fourth Schottky diode (118), said fourth Schottky diode being adapted to pass substantial current only from said second node (120) to said logic output (116).

Claim 6

The circuit of claim 1 or 3, characterized in that said current source means includes a second transistor (60, 80; 1 22) having a second source region, a second drain region and a second control region, and wherein said second source region is directly electrically connected to said second control region, said second source region is directly electrically connected to a second voltage supply (-VsS ) and said second drain region is directly electrically connected to said first node (54, 82, 120).

Claim 7

The circuit of claim 5, characterized in that said electrical load means includes a third transistor (64, 98, 134) having a third source region, a third drain region and a third control region, wherein said third source region is directly electrically connected to said third control region and to said first drain region, and said third drain region is directly electrically connected to said first voltage supply (V D D).

Claim 8

The circuit according to one of the preceding claims, characterized by: I) a first circuit branch (56, 68; 74, 76) between said logic input and a first node (54, 82), said first circuit branch including a first set of Schottky diodes, said first set of Schottky diodes having at least one Schottky diode (56, 74), wherein each of said diodes in said first set have an anode and a cathode, wherein the cathodes of said first set of diodes are each comprised of metal, said first set of diodes being connected in series along said first circuit branch such that substantial current can pass only along said first branch from said logic input (50, 72) to said first node (54, 82); m) a second circuit branch (58, 78) between said first node (54, 82) and said logic input (50, 72), said second circuit branch including a second set of Schottky diodes, said second set including at least one diode (58, 78), wherein each of said second sets of diodes has a cathode and an anode, wherein the cathodes of said second set of diodes are each comprised of metal, and wherein the diodes of said second set are connected in series along said second circuit branch such that substantial current can pass only along said second current branch from said first node to said logic input.

Claim 9

The circuit of claim 7, characterized by: n) a third circuit branch between said logic output (66 or 116) and a second node (120), said third circuit branch including at least one Schottky diode (1 1 4) adapted to pass substantial current only from said logic output (66 or 116) to said second node (120); and o) a fourth circuit branch (118) between said second node (120) and said logic output (66 or 116), said fourth circuit branch including at least one Schottky diode (118) adapted to pass substantial current only from said second node (120) to said logic output (116 or 66).

Claim 10

The circuit of claim 1, characterized by: p) a first circuit branch between said first logic input (86) and a first node (96), said first circuit branch including at least one Schottky diode (88) adapted to pass substantial current only from said first logic input (86) to said first node (96); q) a second circuit branch from said first node (96) to said first logic input (86), said second circuit branch including at least one Schottky diode (92) adapted to pass substantial current only from said first node (96) to said first logic input (86); r) a first current source means (94) for biasing said Schottky diodes in said first and said second current branches; s) a third circuit branch between said second logic input (72) and a second node (82), said third circuit branch including at least one Schottky diode (74) adapted to pass substantial current only from said second logic input (72) to said second node (82); t) a fourth circuit branch between said second node (82) and said second logic input (72), said fourth circuit branch including at least one Schottky diode (78) adapted to pass substantial current only from said second node (82) to said second logic input (72); u) second current source means (80) for biasing said Schottky diodes in said third and said fourth circuit branches; v) a first field effect transistor (FET) (97) having a first source, a first drain and a first control region, wherein said first control region is electrically connected to said first node (96) and said first source region is electrically connected to said voltage reference point (ground); w) a second field effect transistor (FET) (84) having a second control region, a second source region and a second drain region, wherein said second control region is electrically connected to said second node (82) and said second source region is electrically connected to said first drain region; and x) a drain current means (98) electrically connected to said voltage supply (V D D) and to said logic output (100), said drain current means being adapted to supply current to said first (84) and second (97) FETs (Fig. 4).

Claim 11

The circuit of claim 9, characterized in that said drain current means (98) is a third field effect transistor (98) having a third control region, a third source region and a third drain region, and wherein said third drain region is directly electrically connected to said voltage supply (V D D) and said third source region is directly electrically connected to said second drain region and to said third control region.

Claim 12

The circuit of one of the preceding claims, characterized in thatthe substrate is selected from the group consisting of gallium arsenide (GaAs) and indium phosphide (InP).

Claim 13

The circuit of one of the preceding claims, characterized in that said first transistor is a depletion mode metal-semiconductor field effect transistor (MESFET).

Claim 14

The circuit of claim 12, characterized in that said second (60) and third transistors (64) are depletion mode metal-semiconductor field effect transistors (MESFETS).

Claim 15

The circuit according to one of the claims 1 to 11, characterized in that said first transistor is an enhancement mode metal-semiconductor field effect transistor (126) (MESFET), and said current source means includes a resistor (132) (Fig. 6).