Gallium arsenide semiconductor integrated circuit

Abstract

Abstract PURPOSE:To inserr a lvel conversion circuit between 2-stage of series connection E/D inverter circuits so as to descend the low level into a negative potential. CONSTITUTION:A logic signal from a node 10 is inverted by an inverter and its level is subjected to level conversion by a level conversion circuit comprising a normally-off metal-semiconductor FET (MESFET) 5, a Schottky diode 7 and a normally-on MESFET 2. The high level to a level of a node 11 is selected equal to the high level of the internal logic amplitude of an E/D direct coupled FET logic circuit and the low level is brought into a common potential by selecting properly the circuit constant of the conversion circuit and the negative power supply of a node 13. In this case, the normally-off MESFET 6 is turned off completely to a low level of the node 13 regardless of the variation in the thereshold voltage and the inverter comprising the normally-on MESFET 3 and the normally-off MESFET 6 gives always normal inverting operation.

Inventors

• 👤 Hiroyuki Makino
• 👤 博之 牧野
• 👤 Satoshi Takano
• 👤 聡 高野

Bibliographic Details