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US4912745A Expired / Lapsed US ⏱️ 0.0 years remaining

Logic circuit connecting input and output signal lines

Assignee: Gazelle Microcircuits Inc
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Filing: 1988-12-02
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Granted: 1990-03-27
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Expires: 2008-12-02
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Abstract

Abstract This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Inventors

  • 👤 Mark E. Fitzpatrick
  • 👤 Andrew C. Graham

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 06:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/0952; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03K3/353; H03K3/356; H03K3/3565

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 196 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first, second and third transistors; said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal; load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor; said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal; said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal; the control terminals of the first and third transistors being connected to the input signal lead; the output signal lead being connected to the first current handling terminal of the third transistor; and a load device connected between the respective current handling terminals of the first and third transistor and the second voltage supply terminal.
Claim 2
Dependent Claim 196 words
A logic circuit having an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal, comprising: first, second and third transistors; said first transistor having a first current handling terminal, a control terminal, and a second current handling terminal; load means connected between the first voltage supply terminal and the first current handling terminal of the first transistor; said second transistor having a first current handling terminal connected to said first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second current handling terminal; said third transistor having a first current handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal; the control terminals of the first and third transistors being connected to the input signal lead; the output signal lead being connected to the first current handling terminal of the third transistor; and a load device connected between the respective current handling terminals of the first and third transistor and the second voltage supply terminal.
Claim 3
Dependent Claim 18 words
The structure as in claim 1, wherein the second voltage supply terminal is a ground voltage supply terminal.
Claim 4
Dependent Claim 30 words
The structure as in claim 1, wherein the load device is a diode forward biased in the direction from the first voltage supply terminal to the second voltage supply terminal.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-03-26 1993-09-25 1994-03-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-03-26 1997-09-25 1998-03-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-03-26 2001-09-25 2002-03-27 $7700.00 Window Closed / Lapsed

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