US5043607A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output interface circuit between two circuits of different natures
Assignee: Thales SA
•
Filing: 1990-06-19
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Granted: 1991-08-27
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Expires: 2010-06-19
Abstract
Abstract This interface constitutes a matching of the output signals of a first circuit, made of GaAs for example, with the limit values of the input signals of a second digital circuit, made of silicon for example. It has a current amplifier which receives the output signal of the GaAs circuit. The voltages at the high level are controlled by a diode in series with a transistor which is then on. At the low level, the transistor is off, and it is two diodes, in parallel with the transistor, that control the output voltage. This interface is integrated into the chip of the digital circuit, made of GaAs. Single figure.
Inventors
- 👤 Jean-Yves Danckaert
- 👤 Ernesto Perea
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
201 words
An output interface circuit, designed to match output voltages of a first digital circuit on GaAs or group III-V materials with input limit values of a second digital circuit, of an ECL type, on silicon, said output interface circuit comprising: a voltage and current amplifier that receives, at a gate of its input transistor, a signal coming from an output of the first digital circuit; a first stage for controlling a high level of an output voltage of said interface circuit, formed by a diode in series with a switch transistor, said diode connected to a drain of said switch transistor, a gate of said switch transistor receives the signal coming from the voltage and current amplifier, and a source of which is connected to an output of the interface circuit, towards the second digital circuit, a second stage for controlling a low level of said output voltage of said output interface circuit, formed by two diodes in series, mounted in parallel with said first stage and connected to the output of the interface, said first and second stages being supplied between a voltage V dd =0 V applied to the diodes and a call-back voltage of V TT =-2 V.
Claim 2
Dependent Claim
201 words
An output interface circuit, designed to match output voltages of a first digital circuit on GaAs or group III-V materials with input limit values of a second digital circuit, of an ECL type, on silicon, said output interface circuit comprising: a voltage and current amplifier that receives, at a gate of its input transistor, a signal coming from an output of the first digital circuit; a first stage for controlling a high level of an output voltage of said interface circuit, formed by a diode in series with a switch transistor, said diode connected to a drain of said switch transistor, a gate of said switch transistor receives the signal coming from the voltage and current amplifier, and a source of which is connected to an output of the interface circuit, towards the second digital circuit, a second stage for controlling a low level of said output voltage of said output interface circuit, formed by two diodes in series, mounted in parallel with said first stage and connected to the output of the interface, said first and second stages being supplied between a voltage V dd =0 V applied to the diodes and a call-back voltage of V TT =-2 V.
Claim 3
Dependent Claim
45 words
An interface circuit according to claim 1, wherein said switch transistor has dimensions sufficient to have a low voltage drop between drain and source, the high level of the output voltage being controlled by a voltage drop in the diode in series with said transistor.
Claim 4
Dependent Claim
44 words
An interface circuit according to claim 1 wherein, for an input voltage at a low state, the switch transistor is off, the low level of the output voltage being controlled by a drop in voltage in said two diodes in parallel with said transistor.
Claim 5
Dependent Claim
26 words
An interface circuit according to claim 1, 2, or 3, wherein it is integrated into said first digital circuit, and constitutes a matching at output contacts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |