US4743957A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic integrated circuit device formed on compound semiconductor substrate
Assignee: NEC Electronics Corp
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Filing: 1986-05-02
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Granted: 1988-05-10
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Expires: 2006-05-02
Abstract
Abstract A gallium arsenide integrated circuit device compatible with a silicon emitter-coupled logic device includes a plurality of transistors constituting an logic circuit and an output transistor driving an externally provided load in response to an output of the logic circuit. The output transistor has its threshold voltage that is larger in absolute value than the threshold voltages of the remaining transistor, so that an output signal having the ECL level is produced without sacrificing a power consumption and a semiconductor chip area.
Inventors
- 👤 Hiromitsu Hirayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/018542; H03K19/02; H03K19/08; H03K19/094; H03K19/09432; H03K19/09436
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
510 words
A gallium arsenide integrated circuit device comprising: a first power terminal supplied with a ground voltage; a second power terminal supplied with a negative voltage substantially equal to -5.2V; first, second, third and fourth input terminals; first and second output terminals; a latch circuit including: a first resistor connected between said first power terminal and a first node; a second resistor connected between said first node and a second node; a third resistor connected between said first node and a third node; a first Schottky gate field effect transistor having a drain-source path connected between said second node and a fourth node; a second Schottky gate field effect transistor having a drain-source path connected between said second node and a fifth node; a third Schottky gate field effect transistor having a drain-source path connected between said third and fifth nodes; a fourth Schottky gate field effect transistor having a drain-source path connected between said third and fourth nodes; a fifth Schottky gate field effect transistor having a drain-source path connected between said fourth node and a sixth node; a sixth Schottky gate field effect transistor having a drain-source path connected between said fifth node and said sixth node; and a seventh Schottky gate field effect transistor having a drain-source path connected between said sixth node and said second power terminal; said device further comprising: a first level-shift circuit coupling said first input terminal to a gate of said fifth transistor; a second level-shift circuit coupling said second input terminal to a gate of said first transistor; a third level-shift circuit coupling said third input terminal to a gate of said fourth transistor; a fourth level-shift circuit coupling said fourth input terminal to a gate of said sixth transistor; a fifth level-shift circuit coupling said second node to a gate of said third transistor; a sixth level-shift circuit coupling said third node to a gate of said second transistor; a buffer amplifier including first and second input ends connected to the gates of said second and third transistors, respectively, and first and second output ends; an eighth Schottky gate field effect transistor having a gate connected to said first output end of said buffer amplifier and a drain-source path connected between said first power terminal and said first output terminal; and a ninth Schottky gate field effect transistor having a gate connected to said second output end of said buffer amplifier and a drain-source path connected between said first power terminal and said second output terminal; a threshold voltage of each of said first to seventh transistors being within a range from -0.2V to -0.3V and the threshold voltage of each of said eighth and ninth transistors being within a range from -0.6V to -0.9V; whereby first and second output signals each having a logic high level of about -0.7V and an logic low level of about -1.9V are derived respectively from said first and second output terminals when each of said first and second output terminals is connected via a load resistor of 50Ω to a power source of -2.0V.
Claim 2
Dependent Claim
510 words
A gallium arsenide integrated circuit device comprising: a first power terminal supplied with a ground voltage; a second power terminal supplied with a negative voltage substantially equal to -5.2V; first, second, third and fourth input terminals; first and second output terminals; a latch circuit including: a first resistor connected between said first power terminal and a first node; a second resistor connected between said first node and a second node; a third resistor connected between said first node and a third node; a first Schottky gate field effect transistor having a drain-source path connected between said second node and a fourth node; a second Schottky gate field effect transistor having a drain-source path connected between said second node and a fifth node; a third Schottky gate field effect transistor having a drain-source path connected between said third and fifth nodes; a fourth Schottky gate field effect transistor having a drain-source path connected between said third and fourth nodes; a fifth Schottky gate field effect transistor having a drain-source path connected between said fourth node and a sixth node; a sixth Schottky gate field effect transistor having a drain-source path connected between said fifth node and said sixth node; and a seventh Schottky gate field effect transistor having a drain-source path connected between said sixth node and said second power terminal; said device further comprising: a first level-shift circuit coupling said first input terminal to a gate of said fifth transistor; a second level-shift circuit coupling said second input terminal to a gate of said first transistor; a third level-shift circuit coupling said third input terminal to a gate of said fourth transistor; a fourth level-shift circuit coupling said fourth input terminal to a gate of said sixth transistor; a fifth level-shift circuit coupling said second node to a gate of said third transistor; a sixth level-shift circuit coupling said third node to a gate of said second transistor; a buffer amplifier including first and second input ends connected to the gates of said second and third transistors, respectively, and first and second output ends; an eighth Schottky gate field effect transistor having a gate connected to said first output end of said buffer amplifier and a drain-source path connected between said first power terminal and said first output terminal; and a ninth Schottky gate field effect transistor having a gate connected to said second output end of said buffer amplifier and a drain-source path connected between said first power terminal and said second output terminal; a threshold voltage of each of said first to seventh transistors being within a range from -0.2V to -0.3V and the threshold voltage of each of said eighth and ninth transistors being within a range from -0.6V to -0.9V; whereby first and second output signals each having a logic high level of about -0.7V and an logic low level of about -1.9V are derived respectively from said first and second output terminals when each of said first and second output terminals is connected via a load resistor of 50Ω to a power source of -2.0V.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |