Compound semiconductor integrated circuit compatible standard logic signals

Claim 2

A buffer circuit in integrated circuit form comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting said input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply and operatively connected to said buffer circuitry means, a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal and operatively connected to said buffer circuitry means, and means on-chip operatively connected with said buffer circuitry means as part of said integrated circuit for generating a third voltage supply, said means for generating a third voltage supply being independent of radiative coupling in generating said third voltage supply, said circuitry being implemented in compound semiconductor technology.

Claim 3

A buffer circuit in integrated circuit form comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting said input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply and operatively connected to said buffer circuitry means, a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to said buffer circuitry means, and means on-chip operatively connected with said buffer circuitry means as part of said integrated circuit for generating a third voltage supply, said circuitry being implemented in compound semiconductor technology, wherein the circuit is compatible with logic signals thereinto which are substantially standard for a silicon-based integrated circuit.

Claim 4

A buffer circuit in integrated circuit form comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting said input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply and operatively connected to said buffer circuitry means, a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to said buffer circuitry means, and means on-chip operatively connected with said buffer circuitry means as part of said integrated circuit for generating a third voltage supply, said circuitry being implemented in compound semiconductor technology, wherein the circuit is compatible with logic signals thereinto which are substantially standard for a silicon-based integrated circuit.

Claim 5

A buffer circuit in integrated circuit form comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting said input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply and operatively connected to said buffer circuitry means, a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal and operatively connected to said buffer circuitry means, and means on-chip operatively connected with said buffer circuitry means as part of said integrated circuit for generating a third voltage supply, said circuitry being implemented in compound semiconductor technology, wherein the circuit is compatible with logic signals therefrom which are substantially standard for a silicon-based integrated circuit.

Claim 6

A buffer circuit in integrated circuit form comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting said input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply and operatively connected to said buffer circuitry means, a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal and operatively connected to said buffer circuitry means, and means on-chip operatively connected with said buffer circuitry means as part of said integrated circuit for generating a third voltage supply, said circuitry being implemented in compound semiconductor technology, wherein the circuit is compatible with logic signals therefrom which are substantially standard for a silicon-based integrated circuit.

Claim 7

A structure as in claim 3 wherein the circuit is compatible with logic signals thereinto which are substantially standard for a silicon-based integrated circuit.

Claim 8

The structure as in any of claims 1, 2, 3 or 4 wherein said means for generating a third voltage supply comprise means for generating a voltage supply which is more negative than that receivable by said second voltage supply terminal.

Claim 9

The structure as in any of claims 1, 2, 3 or 4 wherein said means for generating a third voltage supply comprise means for generating a voltage supply which is more positive than that receivable by said first voltage supply terminal.

Claim 10

The structure as in any of claims 1, 2, 3 or 4 wherein said means for generating a third voltage supply comprise means for generating a voltage supply different from that receivable by either one of said first and second voltage supply terminals.

Claim 11

An integrated circuit structure comprising: at least one input buffer; at least one output buffer; internal circuitry means interconnecting the input buffer and output buffer; a first voltage supply terminal connected to at least one of the input buffer, output buffer and internal circuitry means; a second voltage supply terminal connected to at least one of the input buffer, output buffer and internal circuitry means; said input buffer, output buffer and internal circuitry means being implemented in compound semiconductor technology; and means on-chip operatively connected with at least one of said input buffer, output buffer and internal circuitry means as part of said integrated circuit for generating a third voltage supply independent of radiative coupling.

Claim 12

An integrated circuit structure comprising: at least one input buffer; at least one output buffer; internal circuitry means interconnecting the input buffer and output buffer; a first voltage supply terminal connected to at least one of the input buffer, output buffer and internal circuitry means; a second voltage supply terminal connected to at least one of the input buffer, output buffer and internal circuitry means; said input buffer, output buffer and internal circuitry means being implemented in compound semiconductor technology; and means on-chip operatively connected with at least one of said input buffer, output buffer and internal circuitry means as part of said integrated circuit for generating a third voltage supply independent of radiative coupling.

Claim 13

The structure as in claim 8 wherein said means for generating a third voltage supply comprise means for generating a voltage supply which is more negative than that receivable by said second voltage supply terminal.

Claim 14

The structure as in claim 8 wherein said means for generating a third voltage supply comprise means for generating a voltage supply which is more positive than that receivable by said first voltage supply terminal.

Claim 15

The structure as in claim 8 wherein said means for generating a third voltage supply comprise means for generating a voltage supply different from that receivable by either one of said first and second voltage supply terminals.

Claim 16

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with logic signals thereinto which are substantially standard for a silicon-based integrated circuit and having a voltage swing of 1.2 volts or more.

Claim 17

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with logic signals thereinto which are substantially standard for a silicon-based integrated circuit and having a voltage swing of 1.2 volts or more.

Claim 18

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with logic signals therefrom which are substantially standard for a silicon-based integrated circuit and having a voltage swing of 1.2 volts or more.

Claim 19

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with logic signals therefrom which are substantially standard for a silicon-based integrated circuit and having a voltage swing of 1.2 volts or more.

Claim 20

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with lower and higher voltage levels of logic signals thereinto which are substantially standard for a silicon-based integrated circuit, the lower logic level being 1.2 volts or less above the voltage receivable by the second voltage supply terminal.

Claim 21

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with lower and higher voltage levels of logic signals thereinto which are substantially standard for a silicon-based integrated circuit, the lower logic level being 1.2 volts or less above the voltage receivable by the second voltage supply terminal.

Claim 22

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with lower and higher voltage levels of logic signals therefrom which are substantially standard for a silicon-based integrated circuit, the lower logic level being 1.2 volts or less above the voltage receivable by the second voltage supply terminal.

Claim 23

A buffer circuit comprising an input signal lead for receiving an input signal, an output signal lead for providing an output signal, buffer circuitry means interconnecting the input signal lead and output signal lead, a first voltage supply terminal for receiving a voltage supply, and operatively connected to the buffer circuitry means, and a second voltage supply terminal for receiving a voltage supply more negative than that receivable by the first voltage supply terminal, and operatively connected to the buffer circuitry means, wherein said circuit is implemented in compound semiconductor technology, and is compatible with lower and higher voltage levels of logic signals therefrom which are substantially standard for a silicon-based integrated circuit, the lower logic level being 1.2 volts or less above the voltage receivable by the second voltage supply terminal.