Elementary logic circuit obtained by means of field effect transistors of gallium arsenide and compatible with the ECL 100 K technology

Claim 1

An elementary logic circuit having Schottky barrier field effect transistors of gallium arsenide and comprising a differential amplifier, a load register R 1 and a transistor T 1 , a first branch of said amplifier being formed by the transistor T 1 , which is of the enhancement type, controlled by an input signal E and connected by its drain, at which a signal S 1 is available, to a first supply voltage terminal (V DD ) through the load resistor R 1 , a load resistor R 2 and an enhancement type transistor T 2 , a second branch of said amplifier being formed by the enhancement transistor T 2 controlled by a reference signal and connected by its drain, at which a signal S 2 is available, to the first supply source terminal (V DD ) through the load resistor R 2 , a transistor T 5 , the coupled sources of the transistors T 1 and T 2 being supplied with current through the transistor T 5 of the charge depletion type connected in a common gate-source arrangement to a second supply potential terminal (V.sub. SS), said circuit further comprising two paired level translator stages, the first of which comprises a diode D 4 and a transistor T 4 connected in a common drain arrangement to the first supply voltage terminal (V DD ), controlled by the signal S 1 of the first branch of the differential amplifier and connected by its source to the anode of the diode D 4 , and the second of which comprises a diode D 3 , and transistor T 3 connected in a common drain arrangement to the first voltage supply terminal (V DD ), controlled by the signal S 2 of the second branch of the differential amplifier and connected by its source to the anode of the diode D 3 , the transistors T 3 and T 4 of the level translator stages being of the enhancement type, further comprising resistors R 3 and R 4 , the cathodes of the diodes D 3 and D 4 of the level translator stages being connected to the second supply voltage terminal (V SS ) through the resistors R 3 and R 4 , which are paired, the output signal S, which is the inverse value of the input signal E of the elementary logic circuit, being provided at the cathode of the diode D 4 of the first level translator stage, the output signal S, complementary to the output signal S, being provided at the cathode of the diode D 3 of the second level translator stage, and the output signal S of the elementary logic circuit comprising a reference signal which controls the transistor T 2 of the second branch of the differential amplifier.