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JPS601922A Expired / Lapsed JP ⏱️ 0.0 years remaining

Level converting circuit

Assignee: NTT Inc
•
Filing: 1983-06-17
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Granted: —
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Expires: 2003-06-17
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Abstract

Abstract PURPOSE:To perform high-speed level conversion by constituting a level converting circuit with an MOS transistor (TR) and a diode to prevent the complication of a production process due to the existence of an MOS circuit and a bipolar circuit on the same substrate and allowing a conversion output level to satisfy the standard value of an ECL level. CONSTITUTION:When an antiphase output signal V0 of a MOS circuit 1 is -5V in a low level VOL, an MOS TR T1 is made conductive, and therefore, the voltage of the anode of a diode D1 is equal to voltage 0V of a power source VCC, and the diode D1 is made conductive, and a diode D2 is made nonconductive. Consequently, the voltage level of an input signal V1 of an ECL circuit 2 is lower than voltage 0V of the power source VCC, and its value is about -0.8V to satisfy a high-level standard value of the ECL level. Meanwhile, when the antiphase output signal V0 of the MOS circuit 1 is in a high level VOH (0V), the MOS TR T1 is made nonconductive, and diodes D1 and D2 are made conductive together. Consequently, the voltage level of the input signal V1 of the ECL circuit 2 is lower than the anode voltage of the diode D1 to satisfy a low-level standard value of the ECL level.

Inventors

  • 👤 Yasuo Omori
  • 👤 康生 大森
  • 👤 Tatsuo Baba
  • 👤 馬場 竜雄

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 05:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507

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