Integrated circuit having field effect transistors

Claim 2

An integrated circuit comprising: a first field effect transistor with an input signal supplied to the gate thereof, and with a voltage of a first source power supply supplied to the source thereof; a second field effect transistor with the source thereof connected to the drain of said first transistor, and with a voltage of a drain power supply supplied to the drain thereof; a clamping circuit connected between the source and the drain of said first transistor; a third field effect transistor with the gate thereof connected to the drain of said first transistor, and with the voltage of said drain power supply supplied to the drain thereof; and a fourth field effect transistor with the drain thereof connected to the source of said third transistor, and with a voltage of a second source power supply supplied to the source thereof.

Claim 3

An integrated circuit as claimed in claim 1, wherein the voltage of said first source power supply is lower than the voltage of said drain power supply, and higher than the voltage of said second source power supply.

Claim 4

An integrated circuit as claimed in claim 1, wherein said transistors are Schottky junction type field effect transistors.

Claim 5

An integrated circuit as claimed in claim 1, wherein each of said transistors is a field effect transistor having a Schottky junction type gate formed on a gallium arsenide substrate.

Claim 6

An integrated circuit as claimed in claim 1, wherein the drain voltage of said third transistor is lower than the threshold value of said transistor.

Claim 7

An integrated circuit as claimed in claim 1, wherein said transistors operate in their saturated regions.

Claim 8

An integrated circuit as claimed in claim 1, wherein said clamping circuit includes a plurality of serially connected diodes.

Claim 9

An integrated circuit as claimed in claim 1, wherein said clamping circuit includes a plurality of transistors, with each of the gates being used as an anode and the short-circuited source and drain being used as a cathode, and the anode and the cathode being serially connected.

Claim 10

In a semiconductor integrated circuit formed on a gallium arsenide substrate and constructed using Schottky junction type field effect transistors, the integrated circuit comprising: an internal logical circuit connected to a first power terminal, which includes a load field effect transistor having its gate and source connected to an internal output terminal, and a plurality of driver field effect transistors connected between said internal output terminal and a second power terminal; and a logic circuit which includes a source follower field effect transistor with its gate connected to said internal output terminal and its drain connected to said first power terminal, a logical level conversion circuit connected between the source terminal of said source follower field effect transistor and a third power terminal, and an output voltage clamping circuit connected between said internal output terminal and said second power terminal.

Claim 11

In a semiconductor integrated circuit formed on a gallium arsenide substrate and constructed using Schottky junction type field effect transistors, the integrated circuit comprising: an internal logical circuit connected to a first power terminal, which includes a load field effect transistor having its gate and source connected to an internal output terminal, and a plurality of driver field effect transistors connected between said internal output terminal and a second power terminal; and a logic circuit which includes a source follower field effect transistor with its gate connected to said internal output terminal and its drain connected to said first power terminal, a logical level conversion circuit connected between the source terminal of said source follower field effect transistor and a third power terminal, and an output voltage clamping circuit connected between said internal output terminal and said second power terminal.

Claim 12

An integrated circuit as claimed in claim 9, wherein said clamping circuit comprises a plurality of diodes mutually connected in the forward direction that are connected between said internal output terminal and said second power terminal.

Claim 13

An integrated circuit as claimed in claim 9, wherein said clamping circuit comprises a plurality of field effect transistors mutually connected in series, with the gate of each field effect transistor used as an anode and with short-circuited drain and source used as a cathode, that are connected between an internal output terminal and said second power terminal.

Claim 14

An integrated circuit as claimed in claim 9, wherein said clamping circuit is formed by two diodes serially connected in forward direction between an internal output terminal and said second power terminal, and wherein a level converting diode is provided, whose anode is connected to the source electrode of said source follower field effect transistor and whose cathode is coupled to said third power terminal.

Claim 15

An integrated circuit comprising: a first logic level conversion circuit using an input terminal as an input thereof and being connected between a first power terminal and a second power terminal; a second logic level conversion circuit using a third power terminal as an input thereof and being connected between the first power terminal and the second power terminal; a differential inverter circuit which uses outputs of said first and second logic level conversion circuits as an input and a reference voltage input, respectively, and which is connected between the first and the second power terminals; a third logic level conversion circuit using an output of said differential inverter circuit as an input thereof and being connected between the first power terminal and the second power terminal; an internal logic circuit which includes a load field effect transistor having a gate and a source thereof connected to an internal output terminal and having a drain thereof connected to the first power terminal, and a driver field effect transistor with a gate thereof connected to an output terminal of said third logic level conversion circuit and a source-drain path thereof connected between said internal output terminal and said third power terminal; and a logic circuit which includes a source follower field effect transistor with a gate thereof connected to said internal output terminal and a drain thereof connected to said first power terminal, a logic level conversion circuit connected between a source terminal of said source follower field effect transistor and said second power terminal, and an output voltage clamping circuit connected between said internal output terminal and said third power terminal.

Claim 16

An integrated circuit comprising: a first logic level conversion circuit using an input terminal as an input thereof and being connected between a first power terminal and a second power terminal; a second logic level conversion circuit using a third power terminal as an input thereof and being connected between the first power terminal and the second power terminal; a differential inverter circuit which uses outputs of said first and second logic level conversion circuits as an input and a reference voltage input, respectively, and which is connected between the first and the second power terminals; a third logic level conversion circuit using an output of said differential inverter circuit as an input thereof and being connected between the first power terminal and the second power terminal; an internal logic circuit which includes a load field effect transistor having a gate and a source thereof connected to an internal output terminal and having a drain thereof connected to the first power terminal, and a driver field effect transistor with a gate thereof connected to an output terminal of said third logic level conversion circuit and a source-drain path thereof connected between said internal output terminal and said third power terminal; and a logic circuit which includes a source follower field effect transistor with a gate thereof connected to said internal output terminal and a drain thereof connected to said first power terminal, a logic level conversion circuit connected between a source terminal of said source follower field effect transistor and said second power terminal, and an output voltage clamping circuit connected between said internal output terminal and said third power terminal.