US4897565A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit using Schottky barrier FETs
Assignee: Toshiba Corp
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Filing: 1988-09-27
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Granted: 1990-01-30
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Expires: 2008-09-27
Abstract
Abstract Disclosed is a logic circuit using Schottky barrier FETs comprising a plurality of circuits connected in series between first and second power supply terminals, the plurality of circuits being DCFL and/or SCFL circuits, the DCFL circuit containing a switching element and a load element, the elements being connected in a direct fashion, and consisting of Schottky barrier FETs, the SCFL circuit being a logic unit containing Schottky barrier FETs connected in a differential fashion, and a potential stabilizing means for stabilizing a potential at the junction point between the adjacent circuits, by supplementally feeding the differential current between the current consumed by the adjacent circuits.
Inventors
- 👤 Shoichi Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:12
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0952
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
81 words
A logic circuit using Schottky barrier FETs comprising: a plurality of DCFL circuits connected in series between first and second power supply terminals, said each DCFL circuits containing a switching element and a load element, said elements consisting of Schottky barrier FETs and connected in a direct fashion; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent DCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent DCFL circuits.
Claim 2
Dependent Claim
81 words
A logic circuit using Schottky barrier FETs comprising: a plurality of DCFL circuits connected in series between first and second power supply terminals, said each DCFL circuits containing a switching element and a load element, said elements consisting of Schottky barrier FETs and connected in a direct fashion; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent DCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent DCFL circuits.
Claim 3
Dependent Claim
25 words
A logic circuit according to claim 1, further comprising a transmitting means for transferring a logic signal from one of said DCFL circuits to another.
Claim 4
Dependent Claim
67 words
A logic circuit according to claim 1, in which said stabilizing means includes a circuit for generating a reference potential; and a Schottky barrier FET coupled at the gate with said reference potential, and outputting as a source follower fashion, said FET being fabricated by the same process as that of the load Schottky barrier FET of the DCFL circuit utilizing the potential at said junction point.
Claim 5
Dependent Claim
71 words
A logic circuit according to claim 1, further comprising an output circuit made up of two Schottky barrier FETs connected in series between said first and second power supply terminals, the gates of said two FETs receiving logic signals one having the inverse logic of the other, the junction point of said two FETs providing a logic signal amounting to the potential difference between said first and second power supply terminals.
Claim 6
Dependent Claim
100 words
A logic circuit using Schottky barrier FETs comprising: at least one DCFL circuit containing a switching element and a load element, both elements being connected in a direct fashion; at least one SCFL circuit being a unit logic containing Schottky barrier FETs connected in a differential manner, said DCFL and SCFL circuits being connected in series between first and second power supply terminals; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent DCFL and SCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent DCFL and SCFL circuits.
Claim 7
Dependent Claim
100 words
A logic circuit using Schottky barrier FETs comprising: at least one DCFL circuit containing a switching element and a load element, both elements being connected in a direct fashion; at least one SCFL circuit being a unit logic containing Schottky barrier FETs connected in a differential manner, said DCFL and SCFL circuits being connected in series between first and second power supply terminals; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent DCFL and SCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent DCFL and SCFL circuits.
Claim 8
Dependent Claim
27 words
A logic circuit according to claim 5, further comprising a transmitting means for transferring a logic signal from one of said DCFL and SCFL circuits to another.
Claim 9
Dependent Claim
81 words
A logic circuit according to claim 5, in which said stabilizing means includes a circuit for generating a reference potential; and a Schottky barrier FET coupled at the gate with said reference potential, and outputting as a source follower fashion, said FET being fabricated by the same process as that of the current source Schottky barrier FET of the circuit utilizing the potential at said junction point, said junction point potential utilizing circuit being one of said DCFL and SCFL circuits.
Claim 10
Dependent Claim
71 words
A logic circuit according to claim 5, further comprising an output circuit made up of two Schottky barrier FETs connected in series between said first and second power supply terminals, the gates of said two FETs receiving logic signals one having the inverse logic of the other, the junction point of said two FETs providing a logic signal amounting to the potential difference between said first and second power supply terminals.
Claim 11
Dependent Claim
73 words
A logic circuit using Schottky barrier FETs comprising: a plurality of SCFL circuits connected in series between first and second power supply terminals, said SCFL circuits being each a unit logic containing Schottky barrier FETs connected in a differential fashion; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent SCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent SCFL circuits.
Claim 12
Dependent Claim
73 words
A logic circuit using Schottky barrier FETs comprising: a plurality of SCFL circuits connected in series between first and second power supply terminals, said SCFL circuits being each a unit logic containing Schottky barrier FETs connected in a differential fashion; and a potential stabilizing means for stabilizing a potential at the junction point between said adjacent SCFL circuits, by supplementally feeding the differential current between the current consumed by said adjacent SCFL circuits.
Claim 13
Dependent Claim
25 words
A logic circuit according to claim 9, further comprising a transmitting means for transferring a logic signal from one of said SCFL circuits to another.
Claim 14
Dependent Claim
68 words
A logic circuit according to claim 9, in which said stabilizing means includes a circuit for generating a reference potential; and a Schottky barrier FET coupled at the gate with said reference potential, and outputting as a source follower fashion, said FET being fabricated by the same process as that of the current source Schottky barrier FET of the SCFL circuit utilizing the potential at said junction point.
Claim 15
Dependent Claim
71 words
A logic circuit according to claim 9, further comprising an output circuit made up of two Schottky barrier FETs connected in series between said first and second power supply terminals, the gates of said two FETs receiving logic signals one having the inverse logic of the other, the junction point of said two FETs providing a logic signal amounting to the potential difference between said first and second power supply terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |