US4812676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mode logic switching circuit having a Schmitt trigger
Assignee: Hewlett Packard Development Co LP
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Filing: 1987-12-21
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Granted: 1989-03-14
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Expires: 2007-12-21
Abstract
Abstract A current mode logic circuit which is implemented with metal-semiconductor field effect transistors (MESFETs) has a triggering circuit which produces hysteresis in the output of the circuit. That is, the output switches abruptly after the input has almost completed a corresponding transition from one logical output to another in a manner characteristic of triggering circuits such as Schmidt triggers. A triggering voltage is generated in response to one of two complementary outputs by triggering transistors configured as a current switch. The triggering voltage delays switching of a logic switching circuit which produces the two outputs which are a logical or boolean function of the input or inputs. The MESFETs are implemented in gallium arsenide technologies and output is equal to the inverted input.
Inventors
- 👤 Ji L. Yang
- 👤 Ronald J. Melanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:22
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
213 words
A current mode logic circuit having an output which changes, between a peak logical high voltage and a peak logical low voltage, comprising: an input circuit means for receiving logical input voltages that shift between a peak logical high voltage and a peak logical low voltage, said shift occurring over a transition time period; output circuit means including first and second output terminals, responsive to a change in current flow, for effecting a transition between said peak logical high voltage and said peak logical low voltage at the respective first and second output terminals corresponding to the logical input voltage; switching circuit means operatively coupled to said output circuit means including first and second transistors operative to be switched between a respective conducting and non-conducting state in response to said shift in input voltage during said transition time period, said change in current flow corresponding to said input voltage; triggering circuit means operatively connected to said first and second transistors responsive to the voltage at one of said first and second output terminals for delaying said switching of said transistors for a predetermined time during the transition time period; and said transfer between the peak logical high and peak logical low output voltage occurs abruptly during a portion of the transition time period.
Claim 2
Dependent Claim
213 words
A current mode logic circuit having an output which changes, between a peak logical high voltage and a peak logical low voltage, comprising: an input circuit means for receiving logical input voltages that shift between a peak logical high voltage and a peak logical low voltage, said shift occurring over a transition time period; output circuit means including first and second output terminals, responsive to a change in current flow, for effecting a transition between said peak logical high voltage and said peak logical low voltage at the respective first and second output terminals corresponding to the logical input voltage; switching circuit means operatively coupled to said output circuit means including first and second transistors operative to be switched between a respective conducting and non-conducting state in response to said shift in input voltage during said transition time period, said change in current flow corresponding to said input voltage; triggering circuit means operatively connected to said first and second transistors responsive to the voltage at one of said first and second output terminals for delaying said switching of said transistors for a predetermined time during the transition time period; and said transfer between the peak logical high and peak logical low output voltage occurs abruptly during a portion of the transition time period.
Claim 3
Dependent Claim
34 words
A current mode logic circuit according to claim 1, wherein said output circuit means further includes a voltage clamping circuit for clamping the logical output voltage at said respective first and second output terminals.
Claim 4
Dependent Claim
57 words
A current mode logic circuit according to claim 1, wherein said triggering circuit means includes means for supplying a reference voltage to said switching circuit means, said reference voltage changing between a low voltage and a high voltage, said reference voltage having a midpoint value at the end of said predetermined time during said transition time period.
Claim 5
Dependent Claim
43 words
A current mode logic circuit according to claim 3, wherein said triggering circuit means includes a third and fourth transistor, said third transistor connected to an output terminal for effecting the transition of said reference voltage between said low voltage and high voltage.
Claim 6
Dependent Claim
45 words
A current mode logic circuit according to claim 4, wherein said third and fourth transistors each have a gate terminal, a source terminal and a drain terminal, said gate terminal of said third transistor is connected to one of said first and second output terminals.
Claim 7
Dependent Claim
26 words
A current mode logic circuit according to claim 5, wherein both of the source terminals of said third and fourth transistors are connected to each other.
Claim 8
Dependent Claim
25 words
A current mode logic circuit according to claim 6, including means for applying a predetermined constant voltage to the gate terminal of the fourth transistor.
References Cited (Backward Citations)
US3596114A
Cited
US3622799A
Cited
US3671764A
Cited
US4443717A
Cited
US4728821A
Cited
US4677315A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |